CY28400-2
100 MHz Differential Buffer for PCI Express and SATA
Features
• CK409 and CK410 companion buffer
• Four differential 0.7V clock output pairs
• OE_INV input for inverting OE, PWRDWN, and
SRC_STP active levels
• Individual OE controls
• Low CTC jitter (< 50 ps)
• Programmable bandwidth
• SRC_STP power management control
• SMBus Block/Byte/Word Read and Write support
• 3.3V operation
• PLL Bypass-configurable
• Divide by 2 programmable outputs
• 28-pin SSOP and TSSOP packages
Functional Description
The CY28400-2 is a differential buffer and serves as a
companion device to the CK409 or CK410 clock generator.
The device is capable of distributing the Serial Reference
Clock (SRC) in PCI Express and SATA implementations.
Block Diagram
Pin Configuration
OE_INV
OE_1, OE_6
SRC_STP
PWRDWN
DIFT1
Output
Control
DIFC1
DIFT2
SCLK
SDATA
SMBus
Controller
Output
Buffer
DIFC2
PLL/BYPASS#
SRCT_IN
SRCC_IN
DIFT5
DIFC5
VDD
SRCT_IN
SRCC_IN
VSS
VDD
DIFT1
DIFC1
OE_1
DIFT2
DIFC2
VDD
PLL/BYPASS#
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD_A
VSS_A
IREF
OE_INV
VDD
DIFT6
DIFC6
0E_6
DIFT5
DIFC5
VDD
HIGH_BW#
SRC_STP
PWRDWN
DIV
HIGH_BW#
DIFT6
DIFC6
28 SSOP/TSSOP
CY28400-2
PLL
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 15
www.SpectraLinear.com
CY28400-2
Pin Description
Pin
2,3
Name
SRCT_IN, SRCC_IN
Type
I,DIF
0.7V Differential inputs
Description
6,7;9,10;20,19; DIF[T/C][2:1] & [6:5]
23,22
8,21
OE_1, OE_6
O,DIF
0.7V Differential Clock Outputs
I,SE
3.3V LVTTL input for enabling differential outputs
Active HIGH if OE_INV = 0
Active LOW if OE_INV = 1
3.3V LVTTL input for selecting PLL bandwidth
0 = High BW, 1 = Low BW
3.3V LVTTL input for Power Down
Active LOW if OE_INV = 0
Active HIGH if OE_INV = 1
3.3V LVTTL input for SRC_STP.
Disables stoppable outputs.
Active LOW if OE_INV = 0
Active HIGH if OE_INV = 1
SMBus Slave Clock Input
A precision resistor is attached to this pin to set the differential output
current
3.3V LVTTL input for selecting fan-out or PLL operation
3.3V Power Supply for PLL
Ground for PLL
Ground for outputs
3.3V power supply for outputs
Input strap for setting polarity of OE_[7:0], SRC_STP, and PWRDWN
17
15
HIGH_BW#
PWRDWN
I,SE
I,SE
16
SRC_STP
I,SE
13
14
26
12
28
27
4
1,5,11,18,24
25
SCLK
SDATA
IREF
PLL/BYPASS#
VDD_A
VSS_A
VSS
VDD
OE_INV
I,SE
I
I
PWR
GND
GND
PWR
I, SE
I/O,OC
Open collector SMBus data
Serial Data Interface
To enhance the flexibility and function of the clock buffer, a
two-signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock
output buffers, can be individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting upon power-up, and therefore use of this
interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface cannot be used during system operation for
power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 1.
The block write and block read protocol is outlined in
Table 2
while
Table 3
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11011100 (DCh).
Table 1. Command Code Definition
Bit
7
(6:0)
0 = Block read or block write operation
1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Description
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
Start
Slave address – 7 bits
Description
Bit
1
2:8
Start
Slave address – 7 bits
Block Read Protocol
Description
Rev 1.0, November 21, 2006
Page 2 of 15
CY28400-2
Table 2. Block Read and Block Write Protocol
(continued)
Block Write Protocol
Bit
9
10
11:18
19
20:27
28
29:36
37
38:45
46
....
....
....
....
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Byte Count from master – 8 bits
Acknowledge from slave
Data byte 0 from master – 8 bits
Acknowledge from slave
Data byte 1 from master – 8 bits
Acknowledge from slave
Data bytes from master/Acknowledge
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
....
....
....
....
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to be
accessed
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0]
of the command code represents the offset of
the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Data byte from slave – 8 bits
Acknowledge from master
Stop
Byte Read Protocol
Description
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge from host
Data byte 0 from slave – 8 bits
Acknowledge from host
Data byte 1 from slave – 8 bits
Acknowledge from host
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Acknowledge from host
Stop
Block Read Protocol
Description
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
Byte 0: Control Register 0
Bit
7
6
@pup
0
0
Name
PWRDWN Drive Mode
SRC_STP Drive Mode
Description
Power Down drive mode
0 = Driven when stopped, 1 = Tri-state
SRC Stop drive mode
0 = Driven when stopped, 1 = Tri-state
Rev 1.0, November 21, 2006
Page 3 of 15
CY28400-2
Byte 0: Control Register 0
(continued)
Bit
5
4
3
2
1
0
@pup
0
0
0
1
1
1
Reserved
Reserved
Reserved
HIGH_BW#
PLL/BYPASS#
SRC_DIV2#
Name
Reserved
Reserved
Reserved
HIGH_BW#
0 = High Bandwidth, 1 = Low bandwidth
PLL/BYPASS#
0 = Fanout buffer, 1 = PLL mode
SRC_DIV2# configures output frequency at half the input frequency
0 = Divided by 2 mode (output = input/2),1 = Normal (output = input)
Description
Byte 1: Control Register 1
Bit
7
6
@pup
1
1
Reserved
OE_6
Name
Reserved
DIF[T/C]6 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
DIF[T/C]5 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
Reserved
Reserved
DIF[T/C]2 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
DIF[T/C]1 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
Reserved
Description
5
1
OE_5
4
3
2
1
1
1
Reserved
Reserved
OE_2
1
1
OE_1
0
1
Reserved
Byte 2: Control Register 2
Bit
7
6
@pup
0
0
Reserved
SRC_STP_DIF[T/C]6
Name
Reserved
Allow Control DIF[T/C]6 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Allow Control DIF[T/C]5 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Reserved
Reserved
Allow Control DIF[T/C]2 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Allow Control DIF[T/C]1 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Reserved
Description
5
0
SRC_STP_DIF[T/C]5
4
3
2
0
0
0
Reserved
Reserved
SRC_STP_DIF[T/C]2
1
0
SRC_STP_DIF[T/C]1
0
0
Reserved
Rev 1.0, November 21, 2006
Page 4 of 15
CY28400-2
Byte 3: Control Register 3
Bit
7
6
5
4
3
2
1
0
@pup
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Byte 4: Vendor ID Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
1
0
0
0
Name
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
Byte 5: Control Register 5
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
OE_INV Clarification
The OE_INV pin is an input strap sampled at power-on. The
functionality of this input is to set the active level polarities for
OE_1, OE_6, PWRDWN, and SRC_STP input pins. ‘Active
HIGH’ indicates the functionality of the input is asserted when
the input voltage level at the pin is high and deasserted when
the voltage level at the input is low. ‘Active LOW’ indicates that
the functionality of the input is asserted when the voltage level
at the input is low and deasserted when the voltage level at the
input pin is high. See V
IH
and V
IL
in the DC Electrical Specifi-
cations for input voltage high and low ranges.
OE_INV
0
1
PWRDWN
Active LOW
Active HIGH
SRC
Active LOW
Active HIGH
OE_1, OE_6
Active HIGH
Active LOW
PWRDWN Clarification
The PWRDWN pin is an asynchronous input used to shut off
all clocks cleanly and instruct the device to evoke power
savings mode. It may be active HIGH or active LOW
depending on the strapped value of the OE_INV input. The
PWRDWN pin should be asserted prior to shutting off the input
clock or power to ensure all clocks shut down in a glitch-free
manner. This signal is synchronized internal to the device prior
to powering down the clock buffer. PWRDWN is an
asynchronous input for powering up the system. When the
PWRDWN pin is asserted, all clocks will be held high or
tri-stated (depending on the state of the control register drive
mode and OE bits) prior to turning off the VCO. All clocks will
start and stop without any abnormal behavior and meet all AC
and DC parameters. This means no glitches, frequency
shifting or amplitude abnormalities among others.
Rev 1.0, November 21, 2006
Page 5 of 15
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