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TDC1049
High-Speed A/D Converter
9-Bit, 30 Msps
Features
•
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•
•
•
•
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30 Msps conversion rate, 15 MHz analog bandwidth
9-Bit resolution and linearity
Sample-and-hold circuit not required
Differential phase 0.5 degrees
Differential gain 1.0%
Overflow flag
Single -5.2V power supply
Differential ECL outputs
Available in a 64-pin DIP, 68-contact LCC and 68-pin
ceramic pin grid array
Description
The TDC1049 is a flash (full-parallel) analog-to-digital
converter capable of converting analog signals with full-
power frequency components up to 15 MHz into 9-bit
words at rates up to 30 Msps (Megasamples Per Second).
A sample-and-hold circuit is not required. All digital inputs
and outputs are differential ECL.
The TDC1049 consists of 512 latching comparators, encod-
ing logic and an output register. A differential convert signal
controls the conversion operation. The outputs can be
connected to give either true or inverted binary or offset
two’s complement fommats.
Applications
• Video data conversion
• Radar data conversion
• High-speed data acquisition
Block Diagram
CONV
CONV
V
IN
R
T
OFS
R
1
R
3
R
5
R
TS
R/2
R
2
1
R/2
R/2
0
2
512 TO 9
ENCODER
OVF,
OVF
D
1-9
D
1-9
18
LATCH
R
R
MID
R
M
R/2
R/2
255
256
R
R
4
R
2
R/2
511
R
BS
R
B
DIFFERENTIAL
COMPARATORS
(512)
65-1049-01
Rev. 1.0.0
TDC1049
PRODUCT SPECIFICATION
Functional Description
General Information
The TDC1049 has three functional sections: a comparator
array, encoding logic and output register. The comparator
array compares the input signal with 512 reference voltages
to produce an N-of-512 code or “thermometer” code.
The comparators referenced to voltages less than the input
signal will be on and those referenced to voltages greater
than the input signal will be off. The encoding logic converts
the N-of-512 code into 9-bit binary data. The output register
holds the output between updates.
A midpoint tap, R
M
, allows the converter to be adjusted for
optimum integral linearity. It can also be used to achieve a
nonlinear transfer function, but adjustment of R
M
is not
required to meet 9-bit linearity. If this node is driven by
external circuitry, it should be driven from a low-impedance
source; if not used, it must be left open.
Parasitic resistances, R1 and R2, introduce offset errors at
the top and bottom of the reference resistor chain. Sense
points, R
TS
, R
BS
and OFS, may be used to reduce the effect
of these offset errors. Overflow Sense (OFS) may be used to
reduce the effect of the offset at the overflow (most positive)
comparator whenever the Overflow (OVF, OVF) flags are
used. Sense points are not required for 9-bit linearity and,
if not used, they must be left open.
Power
For optimum performance, separate analog and digital
power, V
EEA
and V
EED
should be supplied to the TDC1049.
Separate analog and digital power supplies or a common
supply with separate analog and digital paths and high-
frequency decoupling can be used. The return path for the
current drawn from V
EEA
and V
EED
is A
GND
and D
GND
,
respectively. The returns A
GND
and D
GND
should also be
kept separate and connected together at the power supply
terminals. It is recommended that provisions be made on the
printed circuit board for shorting jumpers between analog
and digital ground as close to the A/D converter as possible.
The installation of the jumpers depends upon the printed
circuit board layout and overall system performance once the
system is in operation. The voltage difference between V
EEA
and V
EED
must be less than +0.1V. The same voltage
difference limit applies to the difference between A
GND
and D
GND
. All power and ground inputs to the converter
must be connected.
Convert
The TDC1049 requires a differential ECL clock (CONV and
CONV) signal. The conversion occurs (the comparators are
latched) within t
STO
(Sampling Time Offset) of the rising
edge of CONV. The 512 to 9 encoding is performed on the
falling edge of the CONV signal. The coded result is trans-
ferred to the output register on the next rising edge of CONV.
Data for sample N is available at the output t
D
(Output Delay
Time) after the rising edge of sample N+1.
Analog Input
The TDC1049 uses latching comparators which are con-
nected to the analog inputs V
IN
. For optimal performance,
the source impedance of the driver amplifier should be less
than 25Ω. The input signal will not damage the TDC1049 if
it remains within the range of V
EEA
to +0.5V. If the input
signal is between the V
RT
and V
RB
, the output will be a
binary number between 0 and 511 inclusive. All five analog
inputs must be connected.
Reference
The TDC1049 converts analog signals in the range
V
RB
< V
IN
< V
RT
into digital form. V
RB
(the voltage
applied to R
B
) at the bottom of the reference resistor chain,
and V
RT
(the voltage applied to R
T
) at the top of the refer-
ence resistor chain, should both be between +0.1V and
-2.1V. Within that range, V
RT
must be more positive than
V
RB
. The linearity specification is based upon a 2.0V differ-
ence between V
RT
and V
RB
. The nominal voltages are
V
RT
= 0.0V and V
RB
= -20V. To avoid damage to the con-
verter, the voltage across V
RT
and V
RB
must not exceed
2.2V. A decoupling capacitor is recommended between R
B
and A
GND
. Noise introduced at this point, as well as the
other reference inputs (R
T
, R
TS
, R
M
, R
BS
, OFS), may result
in encoding errors.
Outputs
The outputs of the TDC1049 are differential ECL. The rec-
ommended pull-down resistance is 500Ω to -2V, or a
220/330Ω termination between D
GND
and V
EED
. The OVF
signal indicates that the analog input has exceeded the
threshold of the most positive comparator. Data is held valid
at the output register for at least t
HO
(Output Hold Time)
after the rising edge of CONV. New data becomes valid t
D
after the rising edge of CONV.
No Connects
There are several pins labeled NC (No Connect). These pins
are not connected internally and may be either left open or
connected to analog ground to aid heat transfer from the
package and to reduce electrical noise.
2
PRODUCT SPECIFICATION
TDC1049
Pin Definitions
Pin Number
Pin
Name
V
EEA
V
EED
D
GND
A
GND
R
T
R
TS
R
B
R
BS
R
M
OFS
CONV
CONV
V
IN
D
1
MSB
D
2
–D
8
Bottom-
brazed DIP
46, 48, 51
43, 54
4, 7, 26, 27
Sidebrazed
DIP
14,17,19
11, 22
38, 39, 58,
61
LCC
PGA
Value
-5.2V
-5.2V
0.0V
0.0V
0.0V
0.0V
-2.0V
-2 0V
-1.0V
0.0V
ECL
ECL
0V to
-2V
ECL
ECL
Pin Function Description
Analog Supply Voltage
Digital Supply Voltage
Digital Ground
Analog Ground
Reterence Resistor, Top
Reference Resistor, Top Sense
Reference Resistor, Bottom
Reference Resistor, Bottom Sense
Reference Resistor, Midpoint
Overflow Sense
Convert
Convert, Complement
Analog Signal Input
Most Significant Bit
14, 16, 18, B9, B7, B6,
20, 21
B5
13, 22
41, 65
A3, A10
J2, J11,
H10
13, 14, 19, 8, 25, 45, 46, 9, 27, 48, B2, K4, L4,
20, 40, 57
51, 52
49, 55, 57
K8, L8,
10
8
24
25
17
9
5
6
12, 15, 16,
18, 22
30
32, 34, 36,
58, 60, 62,
64
2
31
55
57
41
40
48
56
60
59
43, 47, 49,
50, 53
35
33, 31, 29,
7, 5, 3, 1
63
34
59
62
44
43
52
61
64
63
L9
K10
K2
K1
L5
L10
J10
K11
46, 50, 53, K3, K5, K6,
54, 58
L7, K9
38
G1
36, 34, 7, F1, E1, D1,
5, 3, 1
C10, D10,
E10, F10
67
37
G10
G2
D
9
LSB
D
1
MSB
D
2
–D
8
ECL
ECL
ECL
Least Significant Bit
Most Significant Bit Complement
33, 35, 37, 32, 30, 28, 6, 35, 33, 31, F2, E2, D2,
59, 61, 63, 1
4, 2, 64
6, 4, 2, 68 D11, E11,
F11, G11
3
28
29
11, 21, 23,
38, 39, 41,
42, 44, 45,
47, 49, 50,
52, 53, 55,
56
62
37
36
9, 10, 12, 13,
15,16, 18,
20, 21, 23,
24, 26, 27,
42, 44, 54
66
40
39
8, 10, 11,
12, 15, 17,
19, 23, 24,
25, 26, 28,
29, 30, 42,
45, 47, 51,
56, 60
H11
H2
H1
B1, C2,
C1, J1, L2,
L3, L6, K7,
C11, B10,
A9, B8,
A8, A7, A6,
A5, B4, A4,
A2
D
9
LSB
OVF
OVF
NC
ECL
ECL
ECL
Open
Least Significant Bit Complement
Ovedlow Output
Overflow Output Complement
No Connect
5
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