LTC1061
High Performance Triple
Universal Filter Building Block
FEATURES
s
s
s
s
DESCRIPTIO
s
s
s
s
s
s
Up to 6th Order Filter Functions with a Single 20-Pin
0.3" Wide Package
Center Frequency Range up to 35kHz
f
O
×
Q Product up to 1MHz
Guaranteed
Center Frequency and Q Accuracy Over
Temperature
Guaranteed
Low Offset Voltages Over Temperature
90dB Signal-to-Noise Ratio
Filter Operates from Single 4.7V Supply and up to
±8V
Supplies
Guaranteed
Filter Specifications with
±5V
Supply and
±2.37V
Supply
Low Power Consumption with Single 5V Supply
Clock Inputs T
2
L and CMOS Compatible
The LTC1061 consists of three high performance, univer-
sal filter building blocks. Each filter building block together
with an external clock and 2 to 5 resistors can produce
various second order functions which are available at its
three output pins. Two out of three always provide low-
pass and bandpass functions while the third output pin
can produce highpass or notch or allpass. The center
frequency of these functions can be tuned with an external
clock or an external clock and a resistor ratio. For Q < 5, the
center frequency ranges from 0.1Hz to 35kHz. For Qs of 10
or above, the center frequency ranges from 0.1Hz to
28kHz.
The LTC1061 can be used with single or dual supplies
ranging from
±2.37V
to
±8V
(or 4.74V to 16V). When the
filter operates with supplies of
±5V
and above, it can
handle input frequencies up to 100kHz.
The LTC1061 is compatible with the LTC1059 single
universal filter and the LTC1060 dual. Higher than 6th
order functions can be obtained by cascading the LTC1061
with the LTC1059 or LTC1060. Any classical filter realiza-
tion can be obtained.
The LTC1061 is manufactured by using Linear Technology’s
enhanced LTCMOS
TM
silicon gate process.
APPLICATI
s
s
S
s
s
High Order, Wide Frequency Range Bandpass,
Lowpass, Notch Filters
Low Power Consumption, Single 5V Supply,
Clock-Tunable Filters
Tracking Filters
Antialiasing Filters
LTCMOS
TM
is a trademark of Linear Technology Corp.
TYPICAL APPLICATI
6th Order, Clock-Tunable, 0.5dB Ripple Chebyshev BP Filter
f
CLK
= 1MHz
2kHz
9.31k
1k
165k
4.99k
165k
V
IN
< 100kHz
1
2
3
4
5
6
7.5V
T
2
CLK IN < 1.2MHz
7
8
9
V
+
= 7.5V
10
LTC1061
20
19
18
17
16
15
14
13
12
11
V
OUT
1061 TA01
78.7k
4.99k
23.7k
49.9k
V
–
= –7.5V
4.99k
165k
5.49k
–20
FILTER GAIN (dB)
–40
–60
–80
–100
0
10
20
30
40
INPUT FREQUENCY GAIN (kHz)
50
LTC1061 • TA02
U
Amplitude Response
0
UO
UO
1
LTC1061
ABSOLUTE
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
LP
A
BP
A
N
A
INV
A
S1
A
AGND
50/100/HOLD
CLK
LS
h
1
2
3
4
5
6
7
8
9
20 LP
B
19 BP
B
18 N
B
17 INV
B
16 S1
B
15 V
–
14 LP
C
13 BP
C
12 HP
C
11 INV
C
Supply Voltage ....................................................... 18V
Power Dissipation............................................. 500mW
Operating Temperature Range
LTC1061AC, LTC1061C ............ –40°C
≤
T
A
≤
85°C
LTC1061AM, LTC1061M ......... –55°C
≤
T
A
≤
125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
ORDER PART
NUMBER
LTC1061AMJ
LTC1061MJ
LTC1061ACJ
LTC1061CJ
LTC1061ACN
LTC1061CN
LTC1061CS
V
+
10
N PACKAGE
J PACKAGE
20-LEAD CERAMIC DIP 20-LEAD PLASTIC DIP
S PACKAGE
20-LEAD PLASTIC SOL
T
JMAX
= 125°C,
θ
JA
= 100°C/W (J)
T
JMAX
= 100°C,
θ
JA
= 100°C/W (N)
T
JMAX
= 100°C,
θ
JA
= 85°C/W (S)
Consult factory for Industrial grade parts
ELECTRICAL CHARACTERISTICS
(Complete Filter)V
S
=
±5V,
T
A
= 25°C, T
2
L clock input level, unless otherwise specified.
PARAMETER
Center Frequency Range, f
O
CONDITIONS
f
O
×
Q
≤
175kHz, Mode 1, V
S
=
±7.5V
f
O
×
Q
≤
1.6MHz, Mode 1, V
S
=
±7.5V
f
O
×
Q
≤
75kHz, Mode 3, V
S
=
±7.5V
f
O
×
Q
≤
1MHz, Mode 3, V
S
=
±7.5V
MIN
TYP
0.1–35k
0.1–25k
0.1–25k
0.1–17k
0–200k
Sides A, B: Mode 1, R1 = R3 = 50k
R2 = 5k, Q = 10, f
CLK
= 250kHz
Pin 7 High.
Side C: Mode 3, R1 = R3 = 50k
R2 = R4 = 5k, f
CLK
= 250kHz
Same as Above, Pin 7 at
Mid-Supplies, f
CLK
= 500kHz
q
q
MAX
UNITS
Hz
Hz
Hz
Hz
Hz
Input Frequency Range
Clock-to-Center Frequency Ratio, f
CLK
/f
O
LTC1061A
LTC1061
50
±0.6%
50
±1.2%
100
±0.6%
100
±1.2%
LTC1061A
LTC1061
Clock-to-Center Frequency Ratio,
Side-to-Side Matching
LTC1061
Q Accuracy
LTC1061A
LTC1061
f
O
Temperature Coefficient
Q Temperature Coefficient
q
q
1.2%
Sides A, B, Mode 1
Side C, Mode 3
f
O
×
Q
≤
50kHz, f
O
× ≤
5kHz
Mode 1, 50:1, f
CLK
< 300kHz
Mode 1, 100:1, f
CLK
< 500kHz
Mode 3, f
CLK
< 500kHz
q
q
±
2
±3
±1
±5
±5
5
5
ppm/°C
ppm/°C
ppm/°C
2
U
%
%
W
U
U
W W
W
LTC1061
ELECTRICAL CHARACTERISTICS
(Complete Filter)V
S
=
±5V,
T
A
= 25°C, T
2
L clock input level, unless otherwise specified.
PARAMETER
DC Offset Voltage
V
OS1
, Figure 23
V
OS2
V
OS2
V
OS3
, LTC1061CN, ACN/LTC1061CS
V
OS3
, LTC1061CN, ACN/LTC1061CS
Clock Feedthrough
Maximum Clock Frequency
Power Supply Current
q
CONDITIONS
q
q
q
q
q
MIN
TYP
2
3
6
3
6
0.4
2.5
MAX
15
30
60
20/25
40/50
UNITS
mV
mV
mV
mV
mV
mV
RMS
MHz
f
CLK
= 250kHz, 50:1
f
CLK
= 500kHz, 100:1
f
CLK
= 250kHz, 50:1
f
CLK
= 500kHz, 100:1
f
CLK
< 1MHz
Mode 1, Q < 5, V
S
≥ ±5
6
8
11
15
mA
mA
(Complete Filter)V
S
=
±2.37V,
T
A
= 25°C, unless otherwise specified.
Center Frequency Range, f
O
Input Frequency Range
Clock-to-Center Frequency Ratio
LTC1061A
LTC1061
LT1061A
LT1061
Q Accuracy
LTC1061A
LTC1061
Maximum Clock Frequency
Power Supply Current
50:1, f
CLK
= 250kHz, Q = 10
Sides A, B: Mode 1
Side C, Mode 3, 250kHz
100:1, f
CLK
= 500kHz, Q = 10
Sides A, B: Mode 1
Side C: Mode 3
Same as Above
f
O
×
Q
≤
120kHz, Mode 1, 50:1
f
O
×
Q
≤
120kHz, Mode 3, 50:1
0.1– 12k
0.1– 10k
0 – 20k
50
±0.6%
50
±1.0%
100
±0.6%
100
±1.0%
Hz
Hz
Hz
±2
±3
700
4.5
6
%
%
kHz
mA
(Internal Op Amps) T
A
= 25°C, unless otherwise specified.
Supply Voltage Range
Voltage Swings
LTC1061A
LTC1061
LTC1061, LTC1061A
Output Short-Circuit Current
Source/Sink
DC Open-Loop Gain
GBW Product
Slew Rate
V
S
=
±5V,
R
L
= 5k (Pins 1,2,13,14,19,20)
V
S
=
±5V,
R
L
= 3.5k (Pins 3,12,18)
q
±2.37
±4.0
±3.8
±3.6
±4.2
±4.2
±9
V
V
V
V
mA
dB
MHz
V/µs
V
S
=
±5V
V
S
=
±5V,
R
L
= 5k
V
S
=
±5V
V
S
=
±5V
40/3
80
3
7
The
q
denotes the specifications which apply over the full operating
temperature range.
3
LTC1061
TYPICAL PERFOR A CE CHARACTERISTICS
Mode 1, Mode 3 (f
CLK
/f
O
)
Deviation vs Q
0.4
0
% DEVIATION (f
CLK
/f
O
)
0.1
% DEVIATION (f
CLK
/f
O
)
V
S
= ±5V
T
A
= 25°C
f
CLK
= 500kHz
DEVIATION OF f
CLK
/f
O
WITH RESPECT TO
Q = 10 MEASUREMENT (%)
V
S
= ±5V
T
A
= 25°C
f
CLK
= 250kHz
f
CLK
/f
O
=
50 (TEST POINT)
–0.4
–0.8
–1.2
–1.6
–2.0
–2.4
.
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
f
CLK
/f
O
=
100 (TEST POINT)
.
0.1
1
IDEAL Q
10
Mode 1: (f
CLK
/f
O
) = 50:1
T
A
= 25°C
f
CLK
/f
O
= 50/1
V
S
= ±2.5V
10
50
Q<5
20
V
S
= ±7.5V
DEVIATION FROM IDEAL Q (%)
DEVIATION FROM IDEAL Q (%)
30
20
10
0
50
30
20
10
0
DEVIATION FROM IDEAL Q (%)
T
A
= 25°C
f
CLK
/f
O
= 50/1
30
20
10
0
0
4
8
50
V
S
= ±5V
20
10 Q<5
12 16 20 24 28 32 36 40
CENTER FREQUENCY (kHz)
1061 G04
Mode 3: (f
CLK
/f
O
) = 100:1
2.5
30
20
10
0
ERROR FROM IDEAL f
CLK
/f
O
(%)
DEVIATION FROM IDEAL Q (%)
V
S
= ±2.5V
10
Q=20
Q=5
20
V
S
= ±7.5V
10
Q=5
Q=1
0.5
0
I
SUPPLY
(mA)
30
20
10
0
0
4
Q=20
V
S
= ±5V
10
Q=5
Q=1
8
12 16 20 24
CENTER FREQUENCY (kHz)
28
32
4
U W
LTC1061 G01
Mode 1, Mode 3 (f
CLK
/f
O
)
Deviation vs Q
Mode 3: Deviation of (f
CLK
/f
O
)
with Respect to Q = 10
Measurement
V
S
= ±5V
T
A
= 25°C
PIN 7 AT 100:1
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.1
1
IDEAL Q
LTC1061 G02
LTC1061 G03
0
f
CLK
/f
O
= 500:1
√R2/R4
= 1/5
(A)
√R2/R4
= 1/2
f
CLK
/f
O
= 200:1
(B)
100
0.1
1
IDEAL Q
10
100
10
100
Mode 1: (f
CLK
/f
O
) = 100:1
20
10
Mode 3: (f
CLK
/f
O
) = 50:1
T
A
= 25°C
f
CLK
/f
O
= 50/1
V
S
= ±7.5V
10 5
5 Q=1
20
2.5
Q=1
V
S
= ±2.5V
Q=20 10
Q<5
V
S
= ±7.5V
Q=20
30
20
10
0
V
S
= ±2.5V
20
10
T
A
= 25°C
f
CLK
/f
O
= 50:1
Q<5
10
Q=5
30
20
10
0
0
4
V
S
= ±5V
10
Q=20
Q=5
30
20
10
20
V
S
= ±5V
10 5
2.5
Q=1
8
12 16 20 24
CENTER FREQUENCY (kHz)
32
28
0
0
4
8
12 16 20 24 28 32 36 40
CENTER FREQUENCY (kHz)
1061 G06
1061 G05
f
CLK
/f
O
vs f
O
2.0
1.5
1.0
Q = 10
T
A
= 25°C
f
CLK
/f
O
= 50/1
V
S
= ±2.5V
MODE 1,
MODE 3
30
V
S
= ±7.5V
V
S
= ±5V
MODE 1
MODE 3
MODE 3
V
S
= ±5V
MODE 1,3
V
S
= ±2.5V
MODE 1,3
Q = 10
T
A
= 25°C
f
CLK
/f
O
= 100/1
MODE 1
27
24
21
18
15
12
9
6
3
0
Power Supply Current vs
Supply Voltage
T
A
= –55°C
T
A
= 25°C
1.5
1.0
0.5
0
0
T
A
= 125°C
V
S
= ±7.5V
MODE 1,3
4
8
12 16 20 24 28 32 36 40
CENTER FREQUENCY (kHz)
1061 G08
0
1
2 3 4 5 6 7 8 9
POWER SUPPLY VOLTAGE (±V)
10
1061 G07
1061 G09
LTC1061
BLOCK DIAGRA S
NA
(3)
CLK
(8)
LEVEL
SHIFT
CLOCK
GENERATOR
INV
A
(4)
TO FILTER A
BP
A
(2)
LP
A
(1)
LEVEL
SHIFT
LEVEL
SHIFT
LEVEL SHIFT
(9)
PI DESCRIPTIO A D APPLICATIO HI TS
Power Supplies (Pins 10, 15)
They should be bypassed with 0.1µF disc ceramic. Low
noise, nonswitching, power supplies are recommended.
The device operates with a single 5V supply, Figure 1, and
with dual supplies. The absolute maximum operating
power supply voltage is
±9V.
Clock and Level shift (Pins 8, 9)
When the LTC1061 operates with symmetrical dual sup-
plies the level shift Pin 9 should be tied to analog ground.
For single 5V supply operation, the level shift pin should be
tied to Pin 15 which will be the system ground. The typical
logic threshold levels of the clock pin are as follows: 1.65V
above the level shift pin for
±5V
supply operation, 1.75V
for
±7.5V
and above, and 1.4V for single 5V supply
operation. The logic threshold levels vary
±100mV
over
the full military temperature range. The recommended
duty cycle of the input clock is 50% although for clock
frequencies below 500kHz the clock “on” time can be as
low as 300ns. The maximum clock frequency for
±5V
supplies and above is 2.4MHz.
S1
A
, S1
B
(Pins 5, 16)
These are voltage input pins. If used, they should be driven
with a source impedance below 5kΩ. when they are not
used, they should be tied to the analog ground Pin 6.
AGND (Pin 6)
When the LTC1061 operates with dual supplies, Pin 6
should be tied to system ground. When the LTC1061
operates with a single positive supply, the analog ground
pin should be tied to 1/2 supply, Figure 1. The positive
input of all the internal op amps, as well as the common
reference of all the internal switches, are internally tied to
the analog ground pin. Because of this, a “clean” ground
is recommended.
U
U
U U
W
–
+
+
Σ
–
S1
A
(5)
NB
(18)
+
∫
+
∫
BP
B
(19)
LP
B
(20)
CLOCK
GENERATOR
INV
B
(17)
TO FILTER B
–
+
+
Σ
–
+
∫
S1
B
(16)
+
∫
HP
C
(12)
CLOCK
GENERATOR
INV
C
(11)
TO FILTER C
BP
C
(13)
LP
C
(14)
–
+
+
∫
+
∫
50/100/
HOLD
(7)
AGND
(6)
V
+
(10)
V
–
(15)
1061 BD
U
5
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