Integrated
Circuit
Systems, Inc.
ICS854057
4:1
OR
2:1 LVDS C
LOCK
M
ULTIPLEXER
WITH
I
NTERNAL
I
NPUT
T
ERMINATION
F
EATURES
•
High speed differential multiplexer. The device can be
configured as either a 4:1 or 2:1 multiplexer
•
Single LVDS output
•
4 selectable PCLK, nPCLK inputs with internal termination
•
PCLK, nPCLK pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
•
Output frequency: >2GHz
•
Part-to-part skew: 200ps (maximum)
•
Propagation delay: 800ps (maximum)
•
Additive phase jitter, RMS: 66fs (typical)
•
2.5V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both, Standard and RoHS/Lead-Free compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS854057 is a 4:1 or 2:1 LVDS Clock Mul-
tiplexer which can operate up to 2GHz and is a
HiPerClockS™
member of the HiPerClockS™ family of High Per-
formance Clock Solutions from ICS. The PCLK,
nPCLK pairs can accept most standard differen-
tial input levels. Internal termination is provided on each dif-
ferential input pair. The ICS854057 operates using a 2.5V sup-
ply voltage. The fully differential architecture and low propa-
gation delay make it ideal for use in high speed multiplexing
applications. The select pins have internal pulldown resistors.
Leaving one input unconnected (pulled to logic low by the in-
ternal resistor) will transform the device into a 2:1 multiplexer.
The SEL1 pin is the most significant bit and the binary num-
ber applied to the select pins will select the same numbered
data input (i.e., 00 selects PCLK0, nPCLK0).
ICS
B
LOCK
D
IAGRAM
VT0
50
PCLK0
nPCLK0
VT1
50
PCLK1
nPCLK1
00
VT2
50
PCLK2
nPCLK2
VT3
50
PCLK3
nPCLK3
SEL1
Pulldown
SEL0
Pulldown
50
50
01
10
11
Q
nQ
50
50
P
IN
A
SSIGNMENT
V
DD
PCLK0
VT0
nPCLK0
SEL1
SEL0
PCLK1
VT1
nPCLK1
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
PCLK3
VT3
nPCLK3
Q
nQ
PCLK2
VT2
nPCLK2
GND
ICS854057
20-Lead TSSOP
4.40mm x 6.50mm x 0.925mm body package
G Package
Top View
854057AG
www.icst.com/products/hiperclocks.html
1
REV. A JULY 18, 2005
Integrated
Circuit
Systems, Inc.
ICS854057
4:1
OR
2:1 LVDS C
LOCK
M
ULTIPLEXER
WITH
I
NTERNAL
I
NPUT
T
ERMINATION
Type
Description
Positive supply pins.
Non-inver ting LVPECL differential clock input. R
T
= 50
Ω
termination to VT0.
Termination input. For LVDS input, leave floating.
R
T
= 50
Ω
termination to VT0.
Inver ting LVPECL differential clock input. R
T
= 50
Ω
termination to VT0
Pulldown
Pulldown
Clock select input. LVCMOS / LVTTL interface levels.
Clock select input. LVCMOS / LVTTL interface levels.
Non-inver ting LVPECL differential clock input. R
T
= 50
Ω
termination to VT1.
Termination input. For LVDS input, leave floating.
R
T
= 50
Ω
termination to VT1.
Inver ting LVPECL differential clock input. R
T
= 50
Ω
termination to VT1.
Power supply ground.
Inver ting LVPECL differential clock input. R
T
= 50
Ω
termination to VT2.
Termination input. For LVDS input, leave floating.
R
T
= 50
Ω
termination to VT2.
Non-inver ting LVPECL differential clock input. R
T
= 50
Ω
termination to VT2.
Differential output pairs. LVDS interface levels.
Inver ting LVPECL differential clock input. R
T
= 50
Ω
termination to VT3.
Termination input. For LVDS input, leave floating.
R
T
= 50
Ω
termination to VT3.
Non-inver ting LVPECL differential clock input. R
T
= 50
Ω
termination to VT3.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 20
2
3
4
5
6
7
8
9
10, 11
12
13
14
15, 16
17
18
19
Name
V
DD
PCLK0
VT0
nPCLK0
SEL1
SEL0
PCLK1
VT1
nPCLK1
GN D
nPCLK2
VT2
PCLK2
nQ, Q
nPCLK3
VT 3
PCLK3
Power
Input
Input
Input
Input
Input
Input
Input
Input
Power
Input
Input
Input
Output
Input
Input
Input
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
T
Parameter
Input Capacitance
Input Pulldown Resistor
Input Termination Resistor
Test Conditions
Minimum
Typical
1.5
50
50
Maximum
Units
pF
kΩ
Ω
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
SEL1
0
0
1
1
SEL0
0
1
0
1
Clock Out
PCLKx/nPCLKx
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK2, nPCLK2
PCLK3, nPCLK3
854057AG
www.icst.com/products/hiperclocks.html
2
REV. A JULY 18, 2005
Integrated
Circuit
Systems, Inc.
ICS854057
4:1
OR
2:1 LVDS C
LOCK
M
ULTIPLEXER
WITH
I
NTERNAL
I
NPUT
T
ERMINATION
4.6V
-0.5V to V
DD
+ 0.5 V
10mA
15mA
73.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
60
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SEL0, SEL1
SEL0, SEL1
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-150
Test Conditions
Minimum
0.7 * V
DD
-0.3
Typical
Maximum
V
DD
+ 0.3
0.3 * V
DD
150
Units
V
V
µA
µA
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
Peak-to-Peak Voltage
Common Mode Input Voltage; NOTE 1, 2
Test Conditions
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-150
0.15
1.2
1.2
V
DD
Minimum
Typical
Maximum
150
Units
µA
µA
V
V
NOTE 1: Common mode input voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is V
DD
+ 0.3V.
854057AG
www.icst.com/products/hiperclocks.html
3
REV. A JULY 18, 2005
Integrated
Circuit
Systems, Inc.
ICS854057
4:1
OR
2:1 LVDS C
LOCK
M
ULTIPLEXER
WITH
I
NTERNAL
I
NPUT
T
ERMINATION
Test Conditions
Minimum
225
1.125
Typical
325
4
1.25
5
Maximum
425
35
1.375
25
Units
mV
mV
V
mV
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Input Skew
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
20% to 80%
≤
700MHz
f = 500MHz
50
47
49
-55
300
622.08MHz,
12kHz - 20MHz
66
40
200
250
53
51
Test Conditions
Minimum
Typical
>2
800
Maximum
Units
GHz
ps
fs
ps
ps
ps
%
%
dBm
t
jit
t
sk(i)
t
sk(pp)
t
R
/ t
F
odc
mux
ISOLATION
NOTE: All parameters are measured at ƒ
≤
1.9GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the output is measured
at the differential cross point.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
854057AG
www.icst.com/products/hiperclocks.html
4
REV. A JULY 18, 2005
Integrated
Circuit
Systems, Inc.
ICS854057
4:1
OR
2:1 LVDS C
LOCK
M
ULTIPLEXER
WITH
I
NTERNAL
I
NPUT
T
ERMINATION
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
-50
-60
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter
@ 622.08MHz
(12kHz to 20MHz)
= 66fs typical
SSB P
HASE
N
OISE
dBc/H
Z
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
500M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
854057AG
www.icst.com/products/hiperclocks.html
5
REV. A JULY 18, 2005
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