54FCT373 Octal Transparent Latch with TRI-STATE Outputs
October 1999
54FCT373
Octal Transparent Latch with TRI-STATE
®
Outputs
General Description
The ’FCT373 consists of eight latches with TRI-STATE out-
puts for bus organized system applications. The flip-flops ap-
pear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup times
is latched. Data appears on the bus when the Output Enable
(OE) is LOW. When OE is HIGH the bus output is in the high
impedance state.
Features
TRI-STATE outputs for bus interfacing
TTL input and output level compatible
CMOS power consumption
Output sink capability of 32 mA, source capability of
12 mA
n
Standard Microcircuit Drawing (SMD) 5962-8764401
n
n
n
n
Ordering Code
Military
54FCT373DMQB
54FCT373FMQB
54FCT373LMQB
Package Number
J20A
W20A
E20A
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
Package Description
20-Lead Ceramic Dual-In-Line
Connection Diagrams
Pin Assignment
for DIP and Flatpak
Pin Assignment
for LCC
DS100957-2
DS100957-1
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Description
Data Inputs
Latch Enable Input
(Active HIGH)
Output Enable Input
(Active LOW)
TRI-STATE Latch
Outputs
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS100957
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54FCT373
Functional Description
The ’FCT373 contains eight D-type latches with TRI-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
n
inputs enters the latches. In this condition the
latches are transparent, i.e., a latch output will change state
each time its D input changes. When LE is LOW, the latches
store the information that was present on the D inputs a
setup time preceding the HIGH-to-LOW transition of LE. The
TRI-STATE buffers are controlled by the Output Enable (OE)
input. When OE is LOW, the buffers are in the bi-state mode.
When OE is HIGH the buffers are in the high impedance
mode but this does not interfere with entering new data into
the latches.
LE
H
H
L
X
Inputs
OE
L
L
L
H
D
n
H
L
X
X
Output
O
n
H
L
O
n
(no change)
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance State
Logic Diagram
DS100957-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
54FCT373
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Ceramic
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
Power-Off State
−65˚C to +150˚C
−55˚C to +125˚C
−55˚C to +175˚C
−0.5V to +7.0V
−0.5V to +7.0V
−30 mA to +5.0 mA
in the HIGH State
Current Applied to Output
in LOW State (Max)
−0.5V to V
CC
twice the rated I
OL
(mA)
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Supply Voltage
Military
−55˚C to +125˚C
+4.5V to +5.5V
Note 1:
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
−0.5V to +5.5V
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
CCQ
∆I
CC
I
CCT
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
54FCT
54FCT
54FCT
54FCT
4.3
2.4
0.2
0.5
5
−5
10
-10
−60
1.5
2.0
5.6
FCT240
Min
2.0
0.8
−1.2
Max
Units
V
V
V
V
V
V
V
µA
µA
µA
µA
mA
mA
mA
mA
Min
Min
Min
Min
Min
Max
Max
Max
Max
Max
Max
Max
Max
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
I
IN
= −18 mA
I
OH
= −300 uA
I
OH
= −12 mA
I
OL
= 300 µA
I
OL
= 32 mA
V
IN
= 5.5V
V
IN
= 0.0V
V
IN
= 5.5V
V
IN
= 0.0V
V
OUT
= 0.0V
V
IN
= 0.2V or V
IN
= 5.3V
V
IN
= 3.4V
V
IN
= 3.4V or V
IN
=GND, OE =
GND, f
I
= 10Mhz, outputs open,
one bit toggling, 50% duty cycle
V
IN
= 5.3V or V
IN
= 0.2V,OE =
GND, f
I
= 10Mhz, outputs open,
one bit toggling, 50% duty cycle
Outputs Open, OE = GND, one bit
toggling, 50% duty Cycle
Input HIGH Current
Input LOW Current
High Impedance Output Current
High Impedance Output Current
Output Short-Circuit Current
Power Supply Current
Power Supply Current
Total Power Supply Current
4.0
I
CCD
Dynamic I
CC
mA
Max
0.25
mA/MHz
Max
3
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54FCT373
AC Electrical Characteristics
Symbol
Parameter
54FCT
T
A
= −55˚C to +125˚C
V
CC
= 4.5V to 5.5V
C
L
= 50 pF
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
1.5
1.5
2.0
2.0
1.5
1.5
1.5
1.5
Max
8.5
8.5
15.0
15.0
13.5
13.5
12.5
12.5
ns
ns
ns
ns
Units
Fig.
No.
Figure 4
Figure 4
Figure 6
Figure 6
AC Operating Requirements
Symbol
Parameter
54FCT
T
A
= −55˚C to +125˚C
V
CC
= 4.5V to 5.5V
C
L
= 50 pF
Min
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
Setup Time, HIGH
or LOW D
n
to LE
Hold Time, HIGH
or LOW D
n
to LE
Pulse Width,
LE HIGH
2.0
2.0
3.0
3.0
6.0
ns
ns
Max
ns
Units
Fig.
No.
Figure 7
Figure 7
Figure 5
Capacitance
Symbol
C
IN
C
OUT
(Note 3)
Parameter
Input Capacitance
Output Capacitance
Max
10
12
Units
pF
pF
Conditions
(T
A
= 25˚C)
V
CC
= 0V
V
CC
= 5.0V
Note 3:
C
OUT
is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
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4
54FCT373
AC Loading
DS100957-8
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
DS100957-4
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
DS100957-5
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
DS100957-6
FIGURE 2. Test Input Signal Levels
Amplitude
3.0V
Rep. Rate
1 MHz
t
w
500 ns
t
r
2.5 ns
t
f
2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100957-7
FIGURE 6. TRI-STATE Output HIGH
and LOW Enable and Disable Times
DS100957-9
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
5
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