- 28-lead 100-mil center DIP (0.600 x 1.4) - contact factory
V
DD
: 5.0 volts
+
10%
Standard Microcircuit Drawing 5962-96891
PRODUCT DESCRIPTION
The UT28F256 amorphous silicon anti-fuse PROM is a high
performance, asynchronous, radiation-hardened,
32K x 8 programmable memory device. The UT28F256 PROM
features fully asychronous operation requiring no external clocks
or timing strobes. An advanced radiation-hardened twin-well
CMOS process technology is used to implement the UT28F256.
The combination of radiation-hardness, fast access time, and low
power consumption make the UT28F256 ideal for high speed
systems designed for operation in radiation environments.
A(14:0)
DECODER
MEMORY
ARRAY
SENSE AMPLIFIER
CE
PE
OE
PROGRAMMING
CONTROL
LOGIC
DQ(7:0)
Figure 1. PROM Block Diagram
2
DEVICE OPERATION
The UT28F256 has three control inputs: Chip Enable (CE),
Program Enable (PE), and Output Enable (OE); fifteen address
inputs, A(14:0); and eight bidirectional data lines, DQ(7:0). CE
is the device enable input that controls chip selection, active, and
standby modes. Asserting CE causes I
DD
to rise to its active value
and decodes the fifteen address inputs to select one of 32,768
words in the memory. PE controls program and read operations.
During a read cycle, OE must be asserted to enable the outputs.
PIN CONFIGURATION
PIN NAMES
A(14:0)
CE
OE
PE
DQ(7:0)
Address
Chip Enable
Output Enable
Program Enable
Data Input/Data Output
Table 1. Device Operation Truth Table
1
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
PE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
OE
X
0
1
1
PE
1
1
0
1
CE
1
0
0
0
I/O MODE
Three-state
Data Out
Data In
Three-state
MODE
Standby
Read
Program
Read
2
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
Thermal resistance, junction-to-case
2
DC input current
LIMITS
-0.3 to 7.0
-0.5 to (V
DD
+ 0.5)
-65 to +150
1.5
+175
3.3
UNITS
V
V
°C
W
°C
°C/W
mA
±
10
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
2. Test per MIL-STD-883, Method 1012, infinite heat sink.
3
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
T
C
V
IN
PARAMETER
Positive supply voltage
Case temperature range
DC input voltage
LIMITS
4.5 to 5.5
-55 to +125
0 to V
DD
UNITS
V
°C
V
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(V
DD
= 5.0V
±
10%; -55°C < T
C
< +125°C)
SYMBOL
V
IH
V
IL
V
OL1
V
OL2
V
OH1
V
OH2
C
IN 1
C
IO 1, 4
I
IN
I
OZ
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
Low-level output voltage
High-level output voltage
High-level output voltage
Input capacitance
(TTL)
(TTL)
I
OL
= 4.0mA, V
DD
= 4.5V (TTL)
I
OL
= 200µA, V
DD
= 4.5V (CMOS)
I
OH
= -200µA, V
DD
= 4.5V (CMOS)
I
OH
= -2.0mA, V
DD
= 4.5V (TTL)
ƒ
= 1MHz, V
DD
= 5.0V
V
IN
= 0V
ƒ
= 1MHz, V
DD
= 5.0V
V
OUT
= 0V
V
IN
= 0V to V
DD
V
O
= 0V to V
DD
V
DD
= 5.5V
OE = 5.5V
V
DD
= 5.5V, V
O
= V
DD
V
DD
= 5.5V, V
O
= 0V
TTL inputs levels (I
OUT
= 0), V
IL
=
0.2V
V
DD
, PE = 5.5V
CMOS input levels V
IL
= V
SS
+0.25V
CE = V
DD
- 0.25 V
IH
= V
DD
- 0.25V
-5
-10
V
DD
-0.1
2.4
15
CONDITION
MINIMUM
2.4
0.8
0.4
V
SS
+ 0.10
MAXIMUM
UNIT
V
V
V
V
V
V
pF
Bidirectional I/O capacitance
15
pF
µA
µA
Input leakage current
Three-state output leakage
current
5
10
I
OS 2,3
I
DD1
(OP)
5
Short-circuit output current
90
-90
mA
mA
Supply current operating
@25.0MHz (40ns product)
@22.2MHz (45ns product)
Supply current standby
125
117
2
mA
mA
mA
I
DD2
(SB)
post-rad
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rad(Si).
1. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. Functional test.
5. Derates at 3.0mA/MHz.
4
READ CYCLE
A combination of PE greater than V
IH
(min), and CE less than
V
IL
(max) defines a read cycle. Read access time is measured
from the latter of device enable, output enable, or valid address
to valid data output.
An address access read is initiated by a change in address inputs
while the chip is enabled with OE asserted and PE deasserted.
Valid data appears on data output, DQ(7:0), after the specified
t
AVQV
is satisfied. Outputs remain active throughout the entire
cycle. As long as device enable and output enable are active, the
address inputs may change at a rate equal to the minimum read
cycle time.
AC CHARACTERISTICS READ CYCLE (Post-Radiation)*
(V
DD
= 5.0V
±
10%; -55°C < T
C
< +125°C)
SYMBOL
t
AVAV1
t
AVQV
t
AXQX2
t
GLQX2
t
GLQV
t
GHQZ
t
ELQX2
t
ELQV
t
EHQZ
PARAMETER
Read cycle time
Read access time
Output hold time
OE-controlled output enable time
OE-controlled access time
OE-controlled output three-state time
CE-controlled output enable time
CE-controlled access time
CE-controlled output three-state time
The chip enable-controlled access is initiated by CE going active
while OE remains asserted, PE remains deasserted, and the
addresses remain stable for the entire cycle. After the specified
t
ELQV
is satisfied, the eight-bit word addressed by A(14:0)
appears at the data outputs DQ(7:0).
Output enable-controlled access is initiated by OE going active
while CE is asserted, PE is deasserted, and the addresses are
stable. Read access time is t
GLQV
unless t
AVQV
or t
ELQV
have
not been satisfied.
28F256-45
MIN
MAX
45
45
0
0
15
15
0
45
15
28F256-40
MIN
MAX
40
40
0
0
15
15
0
40
15
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rads(Si).
1. Functional test.
2. Three-state is defined as a 400mV change from steady-state output voltage.
FPGA/CPLD
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