Datasheet> 器件分类 > 存储> 存储> CY7C1363A-117BGIT

文档预览

CY7C1363A-117BGIT: 产品描述Standard SRAM, 512KX18, 7ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119; 产品类别存储存储; 文件大小817KB，共27页; 制造商Cypress(赛普拉斯)

下载文档详细参数选型对比全文预览

CY7C1363A-117BGIT概述

Standard SRAM, 512KX18, 7ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

CY7C1363A-117BGIT规格参数

参数名称	属性值
零件包装代码	BGA
包装说明	BGA,
针数	119
Reach Compliance Code	unknown
ECCN代码	3A991.B.2.A
最长访问时间	7 ns
其他特性	FLOW-THROUGH ARCHITECTURE
JESD-30 代码	R-PBGA-B119
长度	22 mm
内存密度	9437184 bit
内存集成电路类型	STANDARD SRAM
内存宽度	18
功能数量	1
端子数量	119
字数	524288 words
字数代码	512000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	512KX18
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY
并行/串行	PARALLEL
认证状态	Not Qualified
座面最大高度	2.4 mm
最大供电电压 (Vsup)	3.63 V
最小供电电压 (Vsup)	3.135 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子形式	BALL
端子节距	1.27 mm
端子位置	BOTTOM
宽度	14 mm
Base Number Matches	1

文档预览

下载PDF文档

全文
预览

CY7C1361A

CY7C1363A

256K x 36/512K x 18 Synchronous

Flow-Thru Burst SRAM

Features

•

Fast access times: 6.0, 6.5, 7.0, and 8.0 ns

Fast clock speed: 150, 133, 117, and 100 MHz

Fast OE access times: 3.5 ns and 4.0 ns

Optimal for depth expansion (one cycle chip deselect

to eliminate bus contention)

3.3V –5% and +10% power supply

3.3V or 2.5V I/O supply

5V tolerant inputs except I/Os

Clamp diodes to V

at all inputs and outputs

Common data inputs and data outputs

Byte Write Enable and Global Write control

Multiple chip enables for depth expansion: A package

version and two chip enables for BGA and AJ package

versions

Address pipeline capability

Address, data, and control registers

Internally self-timed Write cycle

Burst control pins (interleaved or linear burst

sequence)

Automatic power-down feature available using ZZ

mode or CE deselect.

JTAG boundary scan for BG and AJ package version

Low-profile 119-bump 14-mm × 22-mm PBGA (Ball Grid

Array) and 100-pin TQFP packages

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE), depth-expansion

Chip Enables (CE

and CE

), burst control inputs (ADSC,

ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and

BWE), and global Write (GW). However, the CE

chip enable

input is only available for the TA package version.

Asynchronous inputs include the Output Enable (OE) and

burst mode control (MODE). The data outputs (Q), enabled by

OE, are also asynchronous.

Addresses and chip enables are registered with either

Address Status Processor (ADSP) or Address Status

Controller (ADSC) input pins. Subsequent burst addresses

can be internally generated as controlled by the Burst Advance

Pin (ADV).

Address, data inputs, and Write controls are registered on-chip

to initiate self-timed Write cycle. Write cycles can be one to

four bytes wide as controlled by the Write control inputs.

Individual byte Write allows individual byte to be written. BWa

controls DQa. BWb controls DQb. BWc controls DQc. BWd

controls DQd. BWa, BWb, BWc, and BWd can be active only

with BWE being LOW. GW being LOW causes all bytes to be

written. The x18 version only has 18 data inputs/outputs (DQa

and DQb) along with BWa and BWb (no BWc, BWd, DQc, and

DQd).

For the TQFP AJ and the BGA package versions, four pins are

used to implement JTAG test capabilities: Test Mode Select

(TMS), Test Data-In (TDI), Test Clock (TCK), and Test

Data-Out (TDO). The JTAG circuitry is used to serially shift

data to and from the device. JTAG inputs use LVTTL/LVCMOS

levels to shift data during this testing mode of operation. The

TA package version does not offer the JTAG capability.

The CY7C1361A and CY7C1363A operate from a +3.3V

power supply. All inputs and outputs are LVTTL-compatible.

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced

triple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high-valued

resistors.

The CY7C1361A and CY7C1363A SRAMs integrate 262,144

× 36 and 524,288 × 18 SRAM cells with advanced

Selection Guide

7C1361A-150

7C1363A-150

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

6.0

480

7C1361A-133

7C1363A-133

6.5

360

7C1361A-117

7C1363A-117

7.0

320

7C1361A-100

7C1363A-100

8.0

270

Unit

Cypress Semiconductor Corporation

Document #: 38-05259 Rev. *B

•

3901 North First Street

•

San Jose

•

CA 95134 • 408-943-2600

Revised September 4, 2002

CY7C1363A-117BGIT相似产品对比

	CY7C1363A-117BGIT	CY7C1363A-117ACT	CY7C1363A-133BGIT	CY7C1363A-117AJIT	CY7C1363A-117AIT	CY7C1363A-117AJCT	CY7C1363A-117BGCT
描述	Standard SRAM, 512KX18, 7ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119	Standard SRAM, 512KX18, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	Standard SRAM, 512KX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119	Standard SRAM, 512KX18, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	Standard SRAM, 512KX18, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	Standard SRAM, 512KX18, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	Standard SRAM, 512KX18, 7ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
零件包装代码	BGA	QFP	BGA	QFP	QFP	QFP	BGA
包装说明	BGA,	LQFP,	BGA,	LQFP,	LQFP,	LQFP,	BGA,
针数	119	100	119	100	100	100	119
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN代码	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
最长访问时间	7 ns	7 ns	6.5 ns	7 ns	7 ns	7 ns	7 ns
其他特性	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE
JESD-30 代码	R-PBGA-B119	R-PQFP-G100	R-PBGA-B119	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PBGA-B119
长度	22 mm	20 mm	22 mm	20 mm	20 mm	20 mm	22 mm
内存密度	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit	9437184 bit
内存集成电路类型	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
内存宽度	18	18	18	18	18	18	18
功能数量	1	1	1	1	1	1	1
端子数量	119	100	119	100	100	100	119
字数	524288 words	524288 words	524288 words	524288 words	524288 words	524288 words	524288 words
字数代码	512000	512000	512000	512000	512000	512000	512000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	85 °C	70 °C	85 °C	85 °C	85 °C	70 °C	70 °C
最低工作温度	-40 °C	-	-40 °C	-40 °C	-40 °C	-	-
组织	512KX18	512KX18	512KX18	512KX18	512KX18	512KX18	512KX18
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	BGA	LQFP	BGA	LQFP	LQFP	LQFP	BGA
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY	FLATPACK, LOW PROFILE	GRID ARRAY	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	GRID ARRAY
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	2.4 mm	1.6 mm	2.4 mm	1.6 mm	1.6 mm	1.6 mm	2.4 mm
最大供电电压 (Vsup)	3.63 V	3.63 V	3.63 V	3.63 V	3.63 V	3.63 V	3.63 V
最小供电电压 (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
端子形式	BALL	GULL WING	BALL	GULL WING	GULL WING	GULL WING	BALL
端子节距	1.27 mm	0.65 mm	1.27 mm	0.65 mm	0.65 mm	0.65 mm	1.27 mm
端子位置	BOTTOM	QUAD	BOTTOM	QUAD	QUAD	QUAD	BOTTOM
宽度	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
Base Number Matches	1	1	1	1	1	-	-

CY7C1363A-117BGIT

CY7C1363A-117BGIT概述

CY7C1363A-117BGIT规格参数

文档预览

CY7C1363A-117BGIT相似产品对比

推荐资源