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4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
4Mb SYNCBURST
™
SRAM
FEATURES
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (V
DD
)
• Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
• SNOOZE MODE for reduced-power standby
• Single-cycle deselect (Pentium
®
BSRAM-compatible)
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL WRITE
• Three chip enables for simple depth expansion
and address pipelining
• Clock-controlled and registered addresses, data
I/Os and control signals
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down for portable applications
• 165-pin FBGA package
• 100-pin TQFP package
• Low capacitive bus loading
• x18, x32, and x36 versions available
MT58L256L18P1, MT58L128L32P1,
MT58L128L36P1; MT58L256V18P1,
MT58L128V32P1, MT58L128V36P1
3.3V V
DD
, 3.3V or 2.5V I/O, Pipelined, Single-Cycle
Deselect
100-PIN TQFP
1
165-BALL FBGA
2
OPTIONS
• Timing (Access/Cycle/MHz)
2.6ns/4.4ns/225 MHz
2.8ns/5ns/200 MHz
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
3.3V I/O
256K x 18
128K x 32
128K x 36
2.5V I/O
256K x 18
128K x 32
128K x 36
• Packages
100-pin TQFP
165-pin FBGA
• Operating Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)**
Part Number Example:
MARKING
-4.4
-5
-6
-7.5
-10
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
2. The 165-ball FBGA is not recommended for new
designs in the 4Mb density.
MT58L256L18P1
MT58L128L32P1
MT58L128L36P1
MT58L256V18P1
MT58L128V32P1
MT58L128V36P1
T
F*
None
IT
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html. The 165-ball
FBGA is not recommended for new designs in the 4Mb density.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
GENERAL DESCRIPTION
The Micron
®
SyncBurst
™
SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
Micron’s 4Mb SyncBurst SRAMs integrate a
256K x 18, 128K x 32, or 128K x 36 SRAM core with ad-
vanced synchronous peripheral circuitry and a 2-bit
burst counter. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single
clock input (CLK). The synchronous inputs include all
addresses, all data inputs, active LOW chip enable
MT58L256L18P1T-6
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
1
©2003, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
FUNCTIONAL BLOCK DIAGRAM
256K x 18
18
SA0, SA1, SA
MODE
ADV#
CLK
ADDRESS
REGISTER
18
16
18
2
SA0, SA1
SA1'
BINARY Q1
COUNTER AND
LOGIC
CLR
Q0
SA0'
ADSC#
ADSP#
BYTE “b”
WRITE REGISTER
9
BYTE “b”
WRITE DRIVER
9
256K x 9 x 2
MEMORY
ARRAY
9
18
SENSE 18
AMPS
BWb#
OUTPUT
18
REGISTERS
OUTPUT
BUFFERS
E
18
BWa#
BWE#
GW#
CE#
CE2
CE2#
OE#
BYTE “a”
WRITE REGISTER
9
BYTE “a”
WRITE DRIVER
DQs
DQPa
DQPb
ENABLE
REGISTER
18
PIPELINED
ENABLE
2
INPUT
REGISTERS
FUNCTIONAL BLOCK DIAGRAM
128K x 32/36
17
SA0, SA1, SA
ADDRESS
REGISTER
17
15
SA0, SA1
17
MODE
ADV#
CLK
Q1
BINARY
COUNTER
SA0'
CLR
Q0
SA1'
ADSC#
ADSP#
BWd#
BYTE “d”
WRITE REGISTER
BYTE “c”
WRITE REGISTER
9
BYTE
“d”
WRITE DRIVER
BYTE
“c”
WRITE DRIVER
BYTE
“b”
WRITE DRIVER
BYTE
“a”
WRITE DRIVER
9
BWc#
9
9
128K x 8 x 4
(x32)
128K x 9 x 4
(x36)
36
SENSE
AMPS
36
OUTPUT
REGISTERS
36
BWb#
BYTE “b”
WRITE REGISTER
9
9
MEMORY
ARRAY
OUTPUT
BUFFERS
E
DQs
DQPa
36
DQPd
BWa#
BWE#
GW#
CE#
CE2
CE2#
OE#
BYTE “a”
WRITE REGISTER
9
9
ENABLE
REGISTER
36
PIPELINED
ENABLE
4
INPUT
REGISTERS
NOTE:
Functional block diagrams illustrate simplified device operation. See truth tables, pin descriptions, and timing diagrams
for detailed information.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
GENERAL DESCRIPTION (continued)
(CE#), two additional chip enables for easy depth ex-
pansion (CE2, CE2#), burst control inputs (ADSC#,
ADSP#, ADV#), byte write enables (BWx#) and global
write (GW#).
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is
also a burst mode input (MODE) that selects between
interleaved and linear burst modes. The data-out (Q),
enabled by OE#, is also asynchronous. WRITE cycles
can be from one to two bytes wide (x18) or from one to
four bytes wide (x32/x36), as controlled by the write
control inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be
internally generated as controlled by the burst advance
input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins and DQPa; BWb# controls DQb
pins and DQPb. During WRITE cycles on the x32 and
x36 devices, BWa# controls DQa pins and DQPa; BWb#
controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. GW#
LOW causes all bytes to be written. Parity bits are only
available on the x18 and x36 versions.
This device incorporates a single-cycle deselect fea-
ture during READ cycles. If the device is immediately
deselected after a READ cycle, the output bus goes to a
High-Z state
t
KQHZ nanoseconds after the rising edge
of clock.
Micron’s 4Mb SyncBurst SRAMs operate from a +3.3V
V
DD
power supply, and all inputs and outputs are TTL-
compatible. Users can choose either a 3.3V or 2.5V I/O
version. The device is ideally suited for Pentium and
PowerPC pipelined systems and systems that benefit
from a very wide, high-speed data bus. The device is
also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-
wide applications.
Please refer to Micron’s Web site (www.micron.com/
sramds)
for the latest data sheet.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
TQFP PIN ASSIGNMENT TABLE
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
x32/x36
NC/DQPc*
DQc
DQc
V
DD
Q
V
SS
NC
DQc
NC
DQc
DQb
DQc
DQb
DQc
V
SS
V
DD
Q
DQb
DQc
DQb
DQc
V
DD
V
DD
NC
V
SS
DQb
DQd
DQb
DQd
V
DD
Q
V
SS
DQb
DQd
DQb
DQd
DQPb
DQd
NC
DQd
x18
NC
NC
NC
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
x18
x32/x36
V
SS
V
DD
Q
NC
NC
NC
DQd
DQd
NC/DQPd*
MODE
SA
SA
SA
SA
SA1
SA0
DNU
DNU
V
SS
V
DD
NF**
NF**
SA
SA
SA
SA
SA
SA
SA
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x32/x36
NC/DQPa*
DQa
DQa
V
DD
Q
V
SS
NC
DQa
NC
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
ZZ
V
DD
NC
V
SS
DQa
DQb
DQa
DQb
V
DD
Q
V
SS
DQa
DQb
DQa
DQb
DQPa
DQb
NC
DQb
x18
NC
NC
NC
PIN #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
x18
x32/x36
V
SS
V
DD
Q
DQb
DQb
NC/DQPb*
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
NC
BWc#
NC
BWd#
CE2
CE#
SA
SA
NC
NC
SA
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
**Pins 43 and 42 are reserved for address expansion, 8Mb and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
Microchip MCU
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