Latch-Up Current.................................................... >200 mA
Operating Range
Device
WCMA4016U1X
Range
Industrial
Ambient
Temperature
–40°C to +85°C
V
CC
2.7V to
3.6V
Product Portfolio
Power Dissipation (Industrial)
V
CC
Range
Product
WCMA4016U1X
V
CC(min.)
V
CC(typ.)
[2]
V
CC(max.)
2.7V
3.0V
3.6V
Power
LL
Speed
(ns)
70
Operating (I
CC
)
Typ.
[2]
7 mA
Maximum
15 mA
Standby (I
SB2
)
Typ.
[2]
2
µA
Maximum
20
µA
Electrical Characteristics
Over the Operating Range
WCMA4016U1X
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
V
CC
Operating Supply
Current
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
,
CMOS Levels
V
CC
= 3.6V
Test Conditions
I
OH
= –1.0 mA
I
OL
= 2.1 mA
V
CC
= 2.7V
V
CC
= 2.7V
V
CC
= 3.6V
V
CC
= 2.7V
2.2
–0.5
–1
–1
±1
+1
7
Min.
2.4
0.4
V
CC
+ 0.5V
0.8
+1
+1
15
Typ.
[2]
Max.
Unit
V
V
V
V
µA
µA
mA
I
OUT
= 0 mA, f = 1 MHz,
CMOS Levels
I
SB1
Automatic CE
Power-Down Current—
CMOS Inputs
CE
1
> V
CC
−0.3V,
CE
2
< 0.3V
V
IN
>V
CC
–0.3V, V
IN
<0.3V)
f = f
MAX
(Address and Data
Only),
f = 0 (OE, WE, BHE and BLE),
V
CC
=3.60V
CE
1
> V
CC
– 0.3V or CE
2
<
0.3V,
V
IN
> V
CC
– 0.3V or V
IN
<
0.3V,
f = 0, V
CC
= 3.60V
LL
1
2
2
20
mA
µA
I
SB2
Automatic CE
Power-Down Current—
CMOS Inputs
LL
2
20
µA
Notes:
1. V
IL(min.)
= –2.0V for pulse durations less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25°C.
2
WCMA4016U1X
.
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ.)
Max.
6
8
Unit
pF
pF
Thermal Resistance
Description
Thermal Resistance
(Junction to Ambient)
[3]
Thermal Resistance
(Junction to Case)
[3]
Test Conditions
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed
circuit board
Symbol
Θ
JA
Θ
JC
BGA
55
16
Units
°C/W
°C/W
AC Test Loads and Waveforms
R1
V
CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
V
CC
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
R1
V
CC
Typ
10%
GND
Rise TIme: 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time: 1 V/ns
(a)
(b)
(c)
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
V
TH
OUTPUT
Parameters
R1
R2
R
TH
V
TH
3.0V
1103
1554
645
1.75V
Unit
Ω
Ω
Ω
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.0V
CE
1
> V
CC
– 0.3V, CE
2
< 0.2V,
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V
L
LL
0
70
ns
ns
Conditions
Min.
1.0
1
Typ.
[2]
Max.
3.6
10
Unit
V
µA
t
CDR[3]
t
R[4]
Chip Deselect to Data
Retention Time
Operation Recovery Time
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
4. Full Device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 10
µs
or stable at V
CC(min.)
>10
µs.
3
WCMA4016U1X
Data Retention Waveform
[5]
DATA RETENTION MODE
V
CC
CE1 or
BHE.BLE
or
CE2
V
CC
, min.
t
CDR
V
DR
> 1.0 V
V
CC
, min.
t
R
Switching Characteristics
Over the Operating Range
[6]
70 ns
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE[8]
t
HZBE
WRITE CYCLE
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
Write Cycle Time
CE
1
LOW and CE
2
HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
70
60
60
0
0
50
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[7, 9]
OE HIGH to High Z
[9]
CE
1
LOW and CE
2
HIGH to Low Z
[7]
CE
1
HIGH and CE
2
LOW to High Z
[7, 9]
CE
1
LOW and CE
2
HIGH to Power-Up
CE
1
HIGH and CE
2
LOW to Power-Down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z
BHE / BLE HIGH to High Z
5
25
0
70
70
10
25
5
25
10
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Unit
Notes:
5. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
OL
/I
OH
and 30 pF load capacitance.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. If both byte enables are toggled together this value is 10ns
9. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
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