VSP2230
SLAS319 – MAY 2001
CCD SIGNAL PROCESSOR
FOR DIGITAL CAMERAS
FEATURES
D
CCD Signal Processing
D
D
D
D
– Correlated Double Sampling (CDS)
– Programmable Black Level Clamping
Programmable Gain Amplifier (PGA)
– –6-dB to 42-dB Gain Ranging
10-Bit Digital Data Output
– Up to 36-MHz Conversion Rate
– No Missing Codes
76-dB Signal-to-Noise Ratio
Portable Operation
– Low Voltage: 2.7 V to 3.6 V
– Low Power: 120 mW (typ) at 3.0 V
– Standby Mode: 6 mW
DESCRIPTION
The VSP2230 is a complete mixed-signal processing IC
for digital cameras that provides signal conditioning and
analog-to-digital conversion for the output of a CCD
array. The primary CCD channel provides correlated
double sampling (CDS) to extract the video information
from the pixels, a –6-dB to 42-dB gain with digital control
for varying illumination conditions, and black level
clamping for an accurate black level reference.
Input signal clamping and offset correction of the input
CDS is also performed. The stable gain control is linear
in dB. Additionally, the black level is quickly recovered
after gain change.
The VSP2230Y is pin-to-pin compatible with the
VSP2260Y (10 bit, 20 MHz) one-chip product.
The VSP2230Y is available in a 48-pin LQFP package
and operates from a single 3-V/3.3-V supply.
VSP2230 block diagram
CLPDM
SHP SHD
SLOAD SCLK SDATA
RESET
ADCCK
DRVDD
VCC
Serial Interface
Input
Clamp
Timing Control
B(0–9)
Analog-to-Digital
Converter
Output
Latch
10-Bit
Digital
Output
CCDIN
Correlated
Double
Sampling (CDS)
Programmable
Gain Amplifier –6 to 42 dB
(PGA)
CCD
Output
Signal
Preblanking
Optical Black (OB)
Level Clamping
Reference Voltage Generator
PBLK
COB
CPLOB
BYPP2 BYP BYPM REFN CM
REFP
DRVGND
GNDA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2001, Texas Instruments Incorporated
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1
VSP2230
SLAS319 – MAY 2001
PACKAGE/ORDERING INFORMATION
PRODUCT
VSP2230Y
VSP2230Y
PACKAGE
48-pin LQFP
48-pin LQFP
PACKAGE OUTLINE
NUMBER
ZZ340
ZZ340
SPECIFIED
TEMPERATURE RANGE
0_C to 85_C
0_C to 85_C
PACKAGE
MARKING
VSP2230Y
VSP2230Y
ORDERING
NUMBER†
VSP2230Y
VSP2230Y/2K
TRANSPORT
MEDIA
250 pcs. Tray
Tape and Reel
† This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., VSP2230CDR).
DEMO BOARD ORDERING INFORMATION
PRODUCT
VSP2230Y
ORDERING NUMBER
DEM-VSP2230Y
pin assignments
48-PIN LQFP PACKAGE
(TOP VIEW)
36 35 34 33 32 31 30 29 28 27 26 25
CCDIN
BYPP2
COB
VCC
GNDA
GNDA
GNDA
GNDA
VCC
VCC
BYPM
BYP
CM
REFP
REFN
V
CC
GNDA
GNDA
NC
NC
RESET
SLOAD
SDATA
SCLK
37
38
39
40
41
42
43
44
45
46
47
48
1
2 3 4
5 6 7
8
9 10 11 12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CLPDM
SHD
SHP
CLPOB
PBLK
V
CC
GNDA
ADCCK
GNDA
DRVGND
DRV
DD
NC – No internal connection
2
NC
NC
B0(LSB)
B1
B2
B3
B4
B5
B6
B7
B8
B9(MSB)
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VSP2230
SLAS319 – MAY 2001
Terminal Functions
TERMINAL
NAME
ADCCK
B0(LSB)
B1
B2
B3
B4
B5
B6
B7
B8
B9(MSB)
BYP
BYPM
BYPP2
CCDIN
CLPDM
CLPOB
CM
COB
DRVDD
DRVGND
GNDA
NC
PBLK
NO.
16
3
4
5
6
7
8
9
10
11
12
31
32
29
30
23
20
37
28
13
14
15, 17, 25, 26,
35, 36, 41, 42
1, 2, 43, 44
19
DI
TYPE†
DI
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
AO
AO
AO
AI
DI
DI
AO
AO
P
P
P
Master clock, See Note 1
A/D converter output, Bit 0 (LSB)
A/D converter output, Bit 1
A/D converter output, Bit 2
A/D converter output, Bit 3
A/D converter output, Bit 4
A/D converter output, Bit 5
A/D converter output, Bit 6
A/D converter output, Bit 7
A/D converter output, Bit 8
A/D converter output, Bit 9 (MSB)
Internal reference C (bypass to ground), See Note 2
Internal reference N (bypass to ground), See Note 3
Internal reference P (bypass to ground), See Note 3
CCD signal input
Dummy pixel clamp pulse (Default = Active Low), See Note 4
Optical black clamp pulse (Default = Active Low), See Note 4
A/D converter common mode voltage (bypass to ground), See Note 2
Optical black clamp loop reference (bypass to ground), See Note 5
Power supply. Exclusively for digital output
Digital ground. Exclusively for digital output
Analog ground
Should be left open
Preblanking
High = Normal operation mode
Low = Preblanking mode: digital output all zero
A/D converter negative reference (bypass to ground), See Note 2
A/D converter positive reference (bypass to ground), See Note 2
Asynchronous system reset (active low)
Clock for serial data shift (triggered at the rising edge)
Serial data input
CDS reference level sampling pulse (Default = Active Low), See Note 4
CDS Data level sampling pulse (Default = Active Low), See Note 4
Serial data latch signal (triggered at the rising edge)
Analog power supply
DESCRIPTION
REFN
REFP
RESET
SCLK
SDATA
SHP
SHD
SLOAD
VCC
39
38
45
48
47
21
22
46
18, 24, 27, 33,
34, 40
AO
AO
DI
DI
DI
DI
DI
DI
P
† Designators in TYPE: P: power supply and ground, DI: digital input, DO: digital output, AI: analog input, AO: analog output
NOTES: 1. There are two options to drive the A/D converter:
a). External drive mode. The master clock (ADCCK) drives A/D converter directly.
b). Internal drive mode. The clock internally generated by on-chip timing control circuit using SHP and SHD signals drives A/D
converter.
2. BYP, CM, REFN, and REFP should be connected to ground using a bypass capacitor (0.1
µF).
Refer to voltage
reference
for details.
3. BYPM, BYPP2 should be connected to ground using a bypass capacitor with a recommend value of 200 pF to 600 pF. However,
this depends on the application environment. Refer to
voltage reference
for details.
4. Refer to
serial interface
for details.
5. COB should be connected to ground using a bypass capacitor with a recommend value of 0.1
µF
to 0.22
µF.
However, this depends
on the application environment. Refer to
optical black level clamp loop
for details.
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3
VSP2230
SLAS319 – MAY 2001
detailed description
introduction
The VSP2230 is a complete mixed-signal IC that contains all of the key features associated with the processing
of the CCD imager output signal in a video camera, a digital still camera, a security camera, or similar
applications. A simplified block diagram is shown on the front page of this data sheet. The VSP2230 includes
a correlated double sampler (CDS), a programmable gain amplifier (PGA), an analog-to-digital converter
(ADC), an input clamp, an optical black (OB) level clamp loop, a serial interface, a timing control, and a reference
voltage generator. We recommend an off-chip emitter follower buffer between the CCD output and the VSP2230
CCDIN input. The PGA gain control, the clock polarity setting, and the operation mode choosing can be made
through the serial interface. All parameters are reset to the default value when the RESET pin goes to low
asynchronously from the clocks.
correlated double sampler (CDS)
The output signal of a CCD imager is sampled twice during one pixel period, one at the reference interval and
the other at the data interval.
Subtracting these two samples, extracts the video information of the pixel as well as removes any noise that
is common—or correlated—to both the intervals.
Thus, a CDS is very important to reduce the reset noise and the low frequency noises that are present on the
CCD output signal. Figure 1 shows the simplified block diagram of the CDS and input clamp.
VSP2230
SHP
C(1) = 5 pF
CCD
Output
CIN
CLPDM
SHD
C(2) = 5 pF
CCDIN
+
OPA
_
SHP
REFN (1.25 V)
Figure 1. Simplified Block Diagram of the CDS and Input Clamp
The CDS is driven through an off-chip coupling capacitor (C
IN
). AC coupling is strongly recommended because
the DC level of the CCD output signal is usually too high (several volts) for the CDS to work properly. A 0.1-µF
capacitor is recommended for C
IN
, however, it depends on the application environment.
Also, an off-chip emitter follower buffer is recommended that can drive more than 10 pF, because the 5 pF of
the sampling capacitor and a few pF of stray capacitance can be seen at the input pin. The analog input signal
range at the CCDIN pin is 1 V
P–P
, and the appropriate common mode voltage for the CDS is around 0.5 V to
1.5 V.
The reference level is sampled during SHP active period, and the voltage level is held on the sampling capacitor
C
(1)
at the trailing edge of SHP. The data level is sampled during SHD active period, and the voltage level is
held on the sampling capacitor C
(2)
at the trailing edge of SHD. Then, the switched-capacitor amplifier performs
the subtraction of these two levels.
4
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VSP2230
SLAS319 – MAY 2001
correlated double sampler (CDS) (continued)
The active polarity of SHP/SHD (active high or active low) can be chosen through the serial interface, refer to
serial interface
for details. The default value of SHP/SHD is active low. However, right after power on, this value
is unknown. For this reason, it must be set to the appropriate value by using the serial interface, or reset to the
default value by the RESET pin. The description and the timing diagrams in this data sheet are all based on the
polarity of active low (default value).
input clamp and dummy pixel clamp
The buffered CCD output is capacitively coupled to the VSP2230. The purpose of the input clamp is to restore
the dc component of the input signal that was lost with the ac-coupling and establish the desired dc bias point
for the CDS. Figure 1 shows the simplified block diagram of the input clamp. The input level is clamped to the
internal reference voltage REFN (1.25 V) during the dummy pixel interval. More specifically, when both CLPDM
and SHP are active, then the dummy clamp function becomes active. If the dummy pixels and/or the CLPDM
pulse are not available in your system, the CLPOB pulse can be used in place of CLPDM as long as the clamping
takes place during black pixels. In this case, both CPLDM pin (actives as same timing as CLPOB) and SHP
become active during the optical black pixel interval, then the dummy clamp function becomes active.
The active polarity of CLPDM and SHP (active high or active low) can be chosen through the serial interface,
refer to
serial interface
for details. The default value of CLPDM and SHP is active low. However, right after power
on, this value is unknown. For this reason, it must be set to the appropriate value by using the serial interface,
or reset to the default value by the RESET pin. The description and timing diagrams in this data sheet are all
based on the polarity of active low (default value).
high performance analog-to-digital converter (ADC)
The analog-to-digital converter (ADC) utilizes a fully differential and pipelined architecture. This ADC is well
suited for low voltage operation, low power consumption requirement, and high-speed applications. It assures
10-bit resolution of the output data with no missing code. The VSP2230 includes the reference voltage generator
for the ADC. REFP (positive reference, pin 38), REFN (negative reference, pin 39), and CM (common-mode
voltage, pin 37) should be bypassed to the ground with a 0.1-µF ceramic capacitor. Do not use this voltage
anywhere else in the system because it affects the stability of these reference levels, and then causes ADC
performance degradation. These are analog output pins, so do not apply voltage from the outside.
programmable gain amplifier (PGA)
Figure 2 shows the characteristics of the PGA gain. The PGA provides a gain range of –6 dB to 42 dB, which
is linear in dB. The gain is controlled by a digital code with 10-bit resolution, and it can be settle through the serial
interface, refer to the
serial interface
section for details. The default value of the gain control code is 128 (PGA
gain = 0 dB). However, right after power on, this value is unknown. For this reason, it must be set to the
appropriate value by using the serial interface, or reset to the default value by the RESET pin.
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