DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD720114
ECOUSB
TM
Series
USB 2.0 HUB CONTROLLER
The
µ
PD720114 is a USB 2.0 hub device that complies with the Universal Serial Bus (USB) Specification Revision
2.0 and works up to 480 Mbps. USB 2.0 compliant transceivers are integrated for upstream and all downstream ports.
The
µ
PD720114 works backward compatible either when any one of the downstream ports is connected to a USB 1.1
compliant device, or when the upstream port is connected to a USB 1.1 compliant host.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
µ
PD720114 User’s Manual: S17463E
FEATURES
•
Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)
•
High-speed or full-speed packet protocol sequencer for Endpoint 0/1
•
4 (Max.) downstream facing ports
•
All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5
Mbps) transaction.
•
Supports split transaction to handle full-speed and low-speed transaction on downstream facing ports when
Hub controller is working in high-speed mode.
•
One Transaction Translator per Hub and supports four non-periodic buffers
•
Supports self-powered and bus-powered mode
•
Supports individual or global over-current detection and individual or ganged power control
•
Supports downstream port status with LED
•
Supports non-removable devices by I/O pin configuration
•
Support Energy Star for PC peripheral system
•
On chip Rpu, Rpd resistors and regulator (for core logic)
•
Low power consumption
•
Use 30 MHz X’tal
•
3.3 V power supply
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S17462EJ2V0DS00 (2nd edition)
Date Published May 2005 NS CP (K)
Printed in Japan
2005
µ
PD720114
ORDERING INFORMATION
Part Number
Package
48-pin plastic TQFP (Fine pitch) (7
×
7)
Remark
Lead-free product
µ
PD720114GA-9EU-A
BLOCK DIAGRAM
To Host/Hub
downstream
facing port
Upstream facing port
UP_PHY
CDR
SERDES
UPC
FS_REP
SIE_2H
ALL_TT
F_TIM
EP1
EP0
CDR
DP(1)_PHY
Downstream facing port #1
DP(2)_PHY
DPC
Downstream facing port #2
DP(3)_PHY
Downstream facing port #3
To Hub/Function
upstream facing port
To Hub/Function
upstream facing port
To Hub/Function
upstream facing port
To Hub/Function
upstream facing port
APLL
X1/X2
OSB
DP(4)_PHY
Downstream facing port #4
2.5V REG
CSB(4:1)
PPB(4:1)
2
Data Sheet S17462EJ2V0DS
µ
PD720114
APLL
ALL_TT
: Generates all clocks of Hub.
: Translates the high-speed transactions (split transactions) for full/low-speed device
to full/low-speed transactions.
ALL_TT buffers the data transfer from either
upstream or downstream direction. For OUT transaction, ALL_TT buffers data from
upstream port and sends it out to the downstream facing ports after speed
conversion from high-speed to full/low-speed. For IN transaction, ALL_TT buffers
data from downstream ports and sends it out to the upstream facing ports after
speed conversion from full/low-speed to high-speed.
CDR
DPC
DP(n)_PHY
EP0
EP1
F_TIM (Frame Timer)
: Data & clock recovery circuit
: Downstream Port Controller handles Port Reset, Enable, Disable, Suspend and
Resume
: Downstream transceiver supports high-speed (480 Mbps), full-speed (12 Mbps), and
low-speed (1.5 Mbps) transaction
: Endpoint 0 controller
: Endpoint 1 controller
: Manages hub’s synchronization by using micro-SOF which is received at upstream
port, and generates SOF packet when full/low-speed device is attached to
downstream facing port.
FS_REP
OSB
2.5V REG
SERDES
SIE_2H
UP_PHY
UPC
: Full/low-speed repeater is enabled when the
µ
PD720114 are worked at full-speed
mode
: Oscillator Block
: On chip 2.5V regulator
: Serializer and Deserializer
: Serial Interface Engine (SIE) controls USB2.0 and 1.1 protocol sequencer.
: Upstream Transceiver supports high-speed (480 Mbps), full-speed (12 Mbps)
transaction
: Upstream Port Controller handles Suspend and Resume
Data Sheet S17462EJ2V0DS
3
µ
PD720114
PIN CONFIGURATION (TOP VIEW)
•
48-pin plastic TQFP (Fine pitch) (7
×
7)
µ
PD720114GA-9EU-A
V
DD33REG
VBUSM
CSB1
PPB1
CSB2
PPB2
V
SS
CSB3
PPB3
CSB4
PPB4
SYSRSTB
48 47 46 45 44 43 42 41 40 39 38 37
V
DD25OUT
V
SSREG
LED4
LED3
LED2
LED1
GREEN
AMBER
V
DD33
X1
X2
V
DD25
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
36
35
34
33
32
31
30
29
28
27
26
25
V
SS
DP4
DM4
V
DD25
DP3
DM3
V
DD33
DP2
DM2
V
SS
DP1
DM1
4
BUS_B
TEST
RREF
AV
SS(R)
AV
DD
AV
SS
AV
DD
V
DD33
DMU
DPU
V
SS
V
DD25
Data Sheet S17462EJ2V0DS
µ
PD720114
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
Pin Name
V
DD25OUT
V
SSREG
LED4
LED3
LED2
LED1
GREEN
AMBER
V
DD33
X1
X2
V
DD25
Pin No.
13
14
15
26
17
18
19
20
21
22
23
24
Pin Name
BUS_B
TEST
RREF
AV
SS
(R)
AV
DD
AV
SS
AV
DD
V
DD33
DMU
DPU
V
SS
V
DD25
Pin No.
25
26
27
28
29
30
31
32
33
34
35
36
Pin Name
DM1
DP1
V
SS
DM2
DP2
V
DD33
DM3
DP3
V
DD25
DM4
DP4
V
SS
Pin No.
37
38
39
40
41
42
43
44
45
46
47
48
Pin Name
SYSRSTB
PPB4
CSB4
PPB3
CSB3
V
SS
PPB2
CSB2
PPB1
CSB1
VBUSM
V
DD33REG
Remark
AV
SS
(R) should be used to connect RREF through 1 % precision reference resistor of 2.43 kΩ.
Data Sheet S17462EJ2V0DS
5
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