Dual VCXO w/3.3V, 2.5V LVPECL
FemtoClock™ PLL
G
ENERAL
D
ESCRIPTION
The 813001I is a dual VCXO + FemtoClock™ Multiplier de-
signed for use in Discrete PLL loops. Two selectable external
VCXO crystals allow the device to be used in multi-rate appli-
cations, where a given line card can be switched, for example,
between 1Gb Ethernet (125MHz system reference clock) and
1Gb Fibre Channel (106.25MHz system reference clock) modes.
Of course, a multitude of other applications are also possible
such as switching between 74.25MHz and 74.175824MHz for
HDTV, switching between SONET, FEC and non FEC rates, etc.
The 813001I is a two stage device – a VCXO followed
by a FemtoClock PLL. The FemtoClock PLL can multiply
the crystal frequency of the VCXO to provide an output
frequency range of 40.83MHz to 640MHz, with a random rms
phase jitter of less than 1ps (12kHz – 20MHz). This phase jitter
performance meets the requirements of 1Gb/10Gb Ethernet,
1Gb, 2Gb, 4Gb and 10Gb Fibre Channel, and SONET up to
OC48. The FemtoClock PLL can also be bypassed if frequen-
cy multiplication is not required. For testing/debug purposes,
de-assertion of the output enable pin will place both Q and nQ
in a high impedance state.
813001I
DATASHEET
F
EATURES
• One 3.3V or 2.5V LVPECL output pair
• Two selectable crystal oscillator interfaces for the VCXO,
one differential clock or one LVCMOS/LVTTL clock inputs
• CLK1/nCLK1 supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Crystal operating frequency range: 14MHz - 24MHz
• VCO range: 490MHz - 640MHz
• Output frequency range: 40.83MHz - 640MHz
• VCXO pull range: ±100ppm (typical)
• Supports the following applications (among others):
SONET, Ethernet, Fibre Channel, HDTV, MPEG
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.84 (typical)
• Supply voltage modes:
V
CC
/V
CCO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in RoHS/Lead-Free compliant package
B
LOCK
D
IAGRAM
VCO_SEL
Pullup
CLK_SEL0
Pulldown
CLK_SEL1
Pullup
CLK0
Pulldown
CLK1
Pulldown
nCLK1
Pullup
XTAL_IN0
00
01
PD
10
(default)
0
Output Divider N
N2:N0
000 ÷1
001 ÷2
010 ÷3
011 ÷4
(default)
100 ÷5
101 ÷6
110 ÷8
111 ÷12
VCO
490-640MHz
1
XTAL_OUT0
XTAL_IN1
Q
nQ
VCXO
11
XTAL_OUT1
VC
M2
Pullup
M1
Pulldown
Pulldown
M0
Pulldown
N2
Pullup
N1
Pullup
N0
Pullup
OE
Feedback Divider M
M2:M0
000 ÷16
001 ÷20
010 ÷22
011 ÷24
100 ÷25
(default)
101 ÷32
110 ÷40
111 MR
P
IN
A
SSIGNMENT
VCO_SEL
N0
N1
N2
V
CCO
Q
nQ
V
EE
V
CCA
V
CC
XTAL_OUT1
XTAL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK_SEL1
CLK_SEL0
OE
M2
M1
M0
CLK1
nCLK1
CLK0
VC
XTAL_IN0
XTAL_OUT0
813001I
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
1
©2015 Integrated Device Technology, Inc.
813001I REVISION A 3/17/15
813001I DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 3
4
5
6, 7
8
9
10
11
12
13
14
15
16
17
18
19, 20
21
22
23
24
Pulldown and Pullup
Name
VCO_SEL
N0, N1
N2
V
CCO
Q, nQ
V
EE
V
CCA
V
CC
XTAL_OUT1,
XTAL_IN1
XTAL_OUT0,
XTAL_IN0
VC
CLK0
nCLK1
CLK1
M0, M1
M2
OE
CLK_SEL0
CLK_SEL1
Input
Input
Input
Power
Ouput
Power
Power
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
Pullup
Pullup
Description
VCO select pin. LVCMOS/LVTTL interface levels.
Output divider select pins. Default value = ÷4.
Pulldown LVCMOS/LVTTL interface levels.
Output supply pin.
Differential output pair. LVPECL interface levels.
Negative supply pin.
Analog supply pin.
Core supply pin.
Parallel resonant crystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
Parallel resonant crystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
VCXO control voltage input.
Pulldown LVCMOS/LVTTL clock input.
Pullup
Inverting differential clock input.
Pulldown Non-inverting differential clock input.
Pulldown Feedback divider select pins. Default value = ÷25.
Pullup LVCMOS/LVTTL interface levels.
Pullup
Pulldown
Pullup
Output enable. When HIGH, the output is active. When LOW, the output is
in a high impedance state. LVCMOS/LVTTL interface levels.
Clock select pin. LVCMOS/LVTTL interface levels. Refer to Table 3.
NOTE: refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_SEL1
0
0
1
1
CLK_SEL0
0
1
0
1
Selected Input
CLK0
CLK1, nCLK1
XTAL0
XTAL1
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
2
REVISION A 3/17/15
813001I DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
70°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
130
10
Units
V
V
V
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, V
CCO
= 2.5V±5%, TA = -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
3.465
2.625
130
10
Units
V
V
V
mA
mA
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 2.5V±5%, TA = -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
2.375
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
2.625
2.625
125
10
Units
V
V
V
mA
mA
REVISION A 3/17/15
3
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
813001I DATA SHEET
T
ABLE
4C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
TA = -40°C
TO
85°C
Symbol
V
IH
V
IL
VC
Parameter
Input High Voltage
Input Low Voltage
VCXO Control Voltage
Input
High Current
N2, M0, M1,
CLK0, CLK_SEL0
N0, N1, M2,
VCO_SEL, CLK_SEL1
N2, M0, M1,
CLK0, CLK_SEL0
N0, N1, M2,
VCO_SEL, CLK_SEL1
V
CC
= V
IN
= 3.465V
or 2.625V
V
CC
= V
IN
= 3.465V
or 2.625V
V
CC
= 3.465V or 2.625V,
V
IN
= 0V
V
CC
= 3.465V or 2.625V,
V
IN
= 0V
V
CC
= 3.465V or 2.625V
-5
-150
-100
100
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= 3.3V
V
CC
= 2.5V
Minimum
2.0
1.7
-0.3
-0.3
0
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
V
CC
150
5
Units
V
V
V
V
V
µA
µA
µA
µA
µA
I
IH
I
IL
Input
Low Current
I
VC
Input Current cƒ V
c
pin
T
ABLE
4D. D
IFFERENTIAL
DC C
HARACTERISTICS
,
TA = -40°C
TO
85°C
Symbol
I
IH
Parameter
CLK1
Input High Current
nCLK1
CLK1
I
IL
V
PP
V
CMR
Input Low Current
nCLK1
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
Test Conditions
V
IN
= V
CC
= 3.465V
or 2.625V
V
IN
= V
CC
= 3.465V
or 2.625V
V
IN
= 0V, V
CC
= 3.465V
or 2.625V
V
IN
= 0V, V
CC
= 3.465V
or 2.625V
Minimum
Typical
Maximum
150
5
-5
-150
0.15
V
EE
+ 0.5
1.3
V
CC
- 0.85
Units
µA
µA
µA
µA
V
V
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended appliations, the maximum input voltage for CLK1, nCLK1 is V
CC
+ 0.3V.
T
ABLE
4E. LVPECL DC C
HARACTERISTICS
,
TA = -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50 to V
CCO
- 2V.
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
4
REVISION A 3/17/15
813001I DATA SHEET
T
ABLE
5A. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
f
OUT
tjit(Ø)
f
VCO
t
R
/ t
F
odc
Parameter
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
PLL VCO Lock Range
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
N÷1
N
≠
÷1
Test Conditions
VCO_SEL = 1
622.08MHz (12kHz - 20MHz)
490
250
43
48
Minimum
40.83
0.84
640
500
57
52
Typical
Maximum
640
Units
MHz
ps
MHz
ps
%
%
NOTE 1: Phase jitter using a crystal interface.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, V
CCO
= 2.5V±5%, TA = -40°C
TO
85°C
Symbol
f
OUT
tjit(Ø)
f
VCO
t
R
/ t
F
odc
Parameter
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
PLL VCO Lock Range
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
N÷1
N
≠
÷1
Test Conditions
VCO_SEL = 1
622.08MHz (12kHz - 20MHz)
490
250
43
48
Minimum
40.83
0.87
640
500
57
52
Typical
Maximum
640
Units
MHz
ps
MHz
ps
%
%
NOTE 1: Phase jitter using a crystal interface.
T
ABLE
5C. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 2.5V±5%, TA = -40°C
TO
85°C
Symbol
f
OUT
tjit(Ø)
f
VCO
t
R
/ t
F
odc
Parameter
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
PLL VCO Lock Range
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
N÷1
N
≠
÷1
Test Conditions
VCO_SEL = 1
622.08MHz (12kHz - 20MHz)
490
250
43
48
Minimum
40.83
1.2
640
500
57
52
Typical
Maximum
640
Units
MHz
ps
MHz
ps
%
%
NOTE 1: Phase jitter using a crystal interface.
REVISION A 3/17/15
5
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
单片机
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