A43L1616
Preliminary
Document Title
1M X 16 Bit X 2 Banks Synchronous DRAM
Revision History
Rev. No.
0.0
0.1
0.2
0.3
1M X 16 Bit X 2 Banks Synchronous DRAM
History
Initial issue
Add 54B Pb-Free CSP package type
Error correction in pin configuration
Add p
art numbering scheme
Issue Date
August 2, 2005
March 15, 2007
July 5, 2007
February 19, 2008
Remark
Preliminary
PRELIMINARY
(February, 2008, Version 0.3)
AMIC Technology, Corp.
A43L1616
Preliminary
Features
Power supply
- VDD: 3.3V VDDQ : 3.3V
LVTTL compatible with multiplexed address
Two banks / Pulse
RAS
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1,2,4,8 & full page)
-
Burst Type (Sequential & Interleave)
Clock Frequency (max) : 167MHz @ CL=3 (-6)
143MHz @ CL=3 (-7)
1M X 16 Bit X 2 Banks Synchronous DRAM
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
Industrial operating temperature range: -40ºC to +85ºC
for -U series.
Available in 54 Balls CSP (8mm X 8mm) and 54-pin
TSOP(II) packages
Package is available to lead free (-F series)
All Pb-free (Lead-free) products are RoHS compliant
General Description
The A43L1616 is 33,554,432 bits synchronous high data
rate Dynamic RAM organized as 2 X 1,048,576 words by
16 bits, fabricated with AMIC’s high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating
frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
Pin Configuration
54 Balls CSP (8 mm x 8 mm)
Top View
1
A
B
C
D
E
F
G
H
J
VSS
DQ
14
DQ
12
DQ
10
DQ
8
UDQM
NC
A8
VSS
54 Ball (6X9) CSP
2
3
7
DQ
15
DQ
13
DQ
11
DQ
9
NC
CLK
NC
A7
A5
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
A6
A4
VDDQ
VSSQ
VDDQ
VSSQ
VDD
8
DQ
0
DQ
2
DQ
4
DQ
6
LDQM
9
VDD
DQ
1
DQ
3
DQ
5
DQ
7
CAS
BA
A0
A3
RAS
NC
A1
A2
WE
CS
A10
VDD
PRELIMINARY
(February, 2008, Version 0.3)
1
AMIC Technology, Corp.
A43L1616
Pin Configuration (continued)
54 TSOP (II)
VDDQ
VSSQ
DQ
14
DQ
13
DQ
11
UDQM
VDDQ
VSSQ
DQ
15
DQ
12
DQ
10
CKE
VSS
VSS
DQ
8
VSS
VDD
LWE
Bank Select
Data Input Register
DQM
DQi
DQ
9
NC
NC
CK
NC
A9
A8
A7
A6
A5
A2
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
A43L1616V
1
VDD
2
DQ
0
3
VDDQ
4
DQ
1
5
DQ
2
6
VSSQ
7
DQ
3
8
DQ
4
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
VSSQ
WE
A10/AP
CAS
RAS
CS
A0
DQ
5
DQ
6
DQ
7
VDD
LDQM
VDDQ
BA
NC
A1
A3
Block Diagram
1M X 16
CLK
1M X 16
ADD
Column Decoder
Latency & Burst Length
LRAS
Programming Register
DQM
LWCBR
LCAS
LRAS
LCBR
LWE
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
PRELIMINARY
(February, 2008, Version 0.3)
2
AMIC Technology, Corp.
A4
A43L1616
Pin Descriptions
Symbol
Name
Description
CLK
CS
System Clock
Chip Select
Active on the positive going edge to sample all inputs.
Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE
Clock Enable
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
A0~A10
Address
Row address : RA0~RA10, Column address: CA0~CA8
Selects bank to be activated during row address latch time.
BA
Bank Select Address
Selects band for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column Address
Strobe
Write Enable
Data Input/Output
Mask
Data Input/Output
Power
Latches column addresses on the positive going edge of the CLK with
CAS
low.
Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power Supply: +3.3V ± 0.3V/Ground
WE
L(U)DQM
DQ
0-15
VDD/VSS
Supply/Ground
VDDQ/VSSQ
NC/RFU
Data Output
Power/Ground
No Connection
Provide isolated Power/Ground to DQs for improved noise immunity.
PRELIMINARY
(February, 2008, Version 0.3)
3
AMIC Technology, Corp.
A43L1616
Absolute Maximum Ratings*
Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to + 4.6V
Voltage on VDD supply relative to VSS (VDD, VDDQ)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to + 4.6V
Storage Temperature (T
STG
) . . . . . . . . . . -55
°
C to +150
°
C
Soldering Temperature X Time (T
SLODER
) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
°
C X 10sec
Power Dissipation (P
D
) . . . . . . . . . . . . . . . . . . . . . . . . 0.8W
Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . . 50mA
*Comments
Permanent device damage may occur if “Absolute
Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended
operating condition.
Exposure to higher than recommended voltage for
extended periods of time could affect device reliability.
Capacitance (T
A
=25°C, f=1MHz)
Parameter
Symbol
Condition
Min
Max
Unit
Input Capacitance
CI1
CI2
A0 to A10, BA
CLK, CKE,
CS
,
RAS
,
CAS
,
WE
, DQM
DQ
0
to DQ
31
2.5
2.5
4.0
3.8
3.8
6.5
pF
pF
pF
Data Input/Output Capacitance
CI/O
DC Electrical Characteristics
Recommend operating conditions
(Voltage referenced to VSS=0V, T
A
= 0ºC to +70ºC for commercial or T
A
=-40ºC to +85ºC for extended)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
DQ Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Output Loading Condition
VDD
VDDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
3
3
2
-0.3
2.4
-
-5
-5
3.3
3.3
3
-
-
-
-
-
3.6
3.6
VDD+0.3
0.8
-
0.4
5
5
V
V
V
V
V
V
μ
A
μ
A
Note 1
I
OH
= -0.1mA
I
OL
= 0.1mA
Note 2
Note 3
See Fig. 1 (Page 6)
Note:
1. V
IL
(min) = -1.5V AC (pulse width
≤
5ns).
2. Any input 0V
≤
VIN
≤
VDD + 0.3V, all other pins are not under test = 0V
3. Dout is disabled, 0V
≤
Vout
≤
VDD
PRELIMINARY
(February, 2008, Version 0.3)
4
AMIC Technology, Corp.
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