SMCT TA32N14A10
Advanced Pulse Power Device
N-MOS VCS, ThinPak
TM
Description
This voltage controlled Solidtron (VCS) discharge switch
utilizes an n-type MOS-Controlled Thyristor mounted on a
ThinPakTM, ceramic "chip-scale" hybrid.
The VCS features the high peak current capability and low On-
state voltage drop common to SCR thyristors combined with
extremely high dI/dt capability. This semiconductor is intended
for the control of high power circuits with the use of very small
amounts of input energy and is ideally suited for capacitor
discharge applications.
The ThinPak
TM
Package is a perforated, metalized ceramic
substrate attached to the silicon using 302
o
C solder. An epoxy
underfill is applied to protect the high voltage termination from
debris. All exterior metal surfaces are tinned with 63pb/37sn
solder providing the user with a circuit ready part. It's small
size and low profile make it extremely attractive to high dI/dt
applications where stray series inductance must be kept to a
minimum.
Anode
Bond Area
Package
Gate Return
Bond Area
Gate Bond Area
Cathode Bond Area
ThinPak
TM
Schematic Symbol
Anode (A)
Features
l
l
l
l
1400V Peak Off-State Voltage
32A Continuous Rating
4kA Surge Current Capability
>100kA/uSec dI/dt Capability
l
l
l
l
<100nSec Turn-On Delay
Low On-State Voltage
MOS Gated Control
Low Inductance Package
Gate (G)
Gate Return (GR)
Cathode (K)
Absolute Maximum Ratings
SYMBOL
Peak Off-State Voltage
Peak Reverse Voltage
Off-State Rate of Change of Voltage Immunity
Continuous Anode Current at 110
o
C
Repetitive Peak Anode Current (Pulse Width=1uSec)
Rate of Change of Current
Continuous Gate-Cathode Voltage
Peak Gate-Cathode Voltage
Minimum Negative Gate-Cathode Voltage Required for Garanteed Off-State
Maximum Junction Temperature
Maximum Soldering Temperature (Installation)
V
DRM
V
RRM
dv/dt
I
A110
I
ASM
dI/dt
V
GKS
V
GKM
V
GK(OFF-MIN)
T
JM
VALUE
1400
-5
5000
32
4000
150
+/-20
+/-25
-5
150
260
UNITS
V
V
V/uSec
A
A
kA/uSec
V
V
V
o
o
C
C
This
SILICON POWER
product is protected by one or more of the following U.S. Patents:
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SMCT TA32N14A10
Advanced Pulse Power Device
N-MOS VCS, ThinPak
TM
Performance Characteristics
Parameters
Anode to Cathode Breakdown Voltage
Anode-Cathode Off-State Current
T
J
=25
o
C unless otherwise specified
Symbol
V
(BR)
i
D
Test Conditions
V
GK
=-5, I
A
=1mA
V
GE
=-5V, V
AK
=1200V
T
C
=25 C
T
C
=150
o
C
Gate-Cathode Turn-On Threshold Voltage
Gate-Cathode Leakage Current
Anode-Cathode On-State Voltage
V
GK(TH)
I
GK(lkg)
V
T
V
AK
=V
GK
, I
AK
=1mA
V
GK
=+/-20V
I
T
=32A, V
GK
=+5V
(See Figures 1,2 & 3)
Input Capacitance
Turn-on Delay Time
Rate of Change of Current
Peak Anode Current
Discharge Event Energy
Turn-on Delay Time
Rate of Change of Current
Peak Anode Current
Discharge Event Energy
Junction to Case Thermal Resistance
Junction to Case Thermal Resistance
C
ISS
t
D(ON)
dI/dt
I
P
E
DIS
t
D(ON)
dI/dt
I
P
E
DIS
R
θJC
R
θJC
0.2uF Capacitor Discharge
T
J
=25 C, V
GK
= -5V to +5V
V
AK
=800V, RG=4.7Ω
L
S
= 7nH (See Figures 4,5 & 6)
0.2uF Capacitor Discharge
T
J
=150
o
C, V
GK
= -5V to +5V
V
AK
=1200V, RG=4.7Ω
L
S
= 7nH (See Figures 4,5 & 6)
Anode (bottom) side cooled (Note 1.)
Cathode-Gate (top) side cooled (Note 2.)
4000
70
0.08
1.5
o
o
o
o
Measurements
Min.
1400
<10
250
0.7
500
T
C
=25
o
C
T
C
=150
o
C
1.5
1.3
6
50
75
3500
32
50
110
100
100
2.0
1.5
100
1000
Typ.
Max.
Units
V
uA
uA
V
nA
V
V
nF
nS
kA/uSec
A
mJ
nS
kA/uSec
A
mJ
C/W
C/W
Notes:
1. Case Exterior Assumed to be 0.002" of 63sn/37pb solder applied directly to Anode. (See Figure 7.)
2. Case Exterior Assummed to be 0.002" of 63sn/37pb solder applied directly to cathode bond area of thinPak. (See Figure 7.)
Typical Performance Curves
(unless otherwise specified)
Figure 1.
On-State Characteristics
Figure 2.
On-State Characteristics
Figure 3.
Predicted High Current On-State Characteristics
SMCT TA32N14A10
Advanced Pulse Power Device
N-MOS VCS, ThinPak
TM
Typical Performance Curves
(Continued)
Figure 4.
Turn-On Delay Characteristics
R
G
=4.7Ω - 500Ω, T
J
=25
o
C
Figure 5.
Turn-On Delay Characteristics
R
G
=4.7Ω & 50Ω, T
J
=25
o
C & 150
o
C
Figure 6.
0.2uF Discharge Pulse Performance Characteristics (See Figure 9.)
Figure 7.
Transient Thermal Impedance Response
SMCT TA32N14A10
Advanced Pulse Power Device
N-MOS VCS, ThinPak
TM
Typical Performance Curves
(Continued)
Figure 8.
Pulses to Failure (Pulse Widths < 100uSec)
Test Circuit and Waveforms
L
SERIES (TOTAL)
l
L
SERIES(TOTAL)
is caculated using
C=0.2uF
+
R
G
Gate
Driver
+5V
-5V
1 / (f 2π)
2
C
where f = frequency of I
A
(See Figure 10)
DUT
-
Supply
Voltage
l
R
SENSE
is a calibrated
Current Viewing Resistor (CVR)
R
SENSE
= 0.010Ω
Figure 9.
0.2uF Pulsed Discharge Circuit Schematic
T
D(ON)
10%
0 Ref.
V
GK
V
AK
90%
I
P
dI/dt
- 10% to 50% of I
A
l
The waveform shown is
representative of one produced using a
very low inductance circuit (<10nH).
l
V
GK
is held positive until I
A
oscillations have ended ( I
A
=0).
I
A
0 Ref.
Figure 10.
0.2uF Pulsed Discharge Circuit Waveforms
SMCT TA32N14A10
Advanced Pulse Power Device
N-MOS VCS, ThinPak
TM
Application Notes
A1.
Junction Temperature Calculation
The figure below shows a lump model of the thermal properties of the size 4 thinPak packaged VCS, from the 2-mil solder
on the top of the lid on the left to the 2-mil solder on the bottom of the device on the right. By adding the user's lump model
of the rest of the thermal system the user can calculate the junction and case temperature rise under any operating
condition.
Anode
(Bottom) Side
Interface
Cathode-Gate
(Top) Side
Interface
Device
Junction
A2.
Calculation of Pulses to Failure for Intermediate/Long Pulse Widths
The user may calculate the Number of Pulses to failure (N
F
) for long to intermedeiate pulse widths (not covered in the
typical performance curve section) by applying the junction temperature rise (dT), calculated as described in A1, to the
formula N
F
=(300/dT)9 .
A3.
Use of Gate Return Bond Area.
The MCT was designed for high di/dt applications. An independent cathode connection or "Gate Return Bond Area" was
provided to minimize the effects of rapidly changing Anode-Cathode current on the Gate control voltage, (V=L*di/dt). It is
therefore, critcal that the user utilize the Gate Return Bond Area as the point at which the gate driver reference (return) is
attached to the VCS device.
Packaging and Handling
Package Dimensions
1. All metal surfaces are tinned using 63pb/37sn
solder.
2. Installation reflow temperature should not exceed
260
o
C or internal package degradation may result.
3. Package may be cooled from either top or bottom
(See Figures 7 & A1 Application Notes.)
4. As with all MOS gated devices, proper handling
procedures must be observed to prevent electrostatic
discharge which may result in permanent damage to
the gate of the device
Top
Cathode-Gate
Bottom
Anode
Side
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