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GTLP6C816A GTLP/LVTTL 1:6 Clock Driver
August 1998
Revised December 2000
GTLP6C816A
GTLP/LVTTL 1:6 Clock Driver
General Description
The GTLP6C816A is a clock driver that provides LVTTL to
GTLP signal level translation (and vice versa). The device
provides a high speed interface between cards operating at
LVTTL logic levels and a backplane operating at GTL(P)
logic levels. High speed backplane operation is a direct
result of GTLP’s reduced output swing (
<
1V), reduced input
threshold levels and output edge rate control. The edge
rate control minimizes bus settling time. GTLP is a Fairchild
Semiconductor derivative of the Gunning Transceiver logic
(GTL) JEDEC standard JESD8-3.
Fairchild’s GTL(P) has internal edge-rate control and is
process, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s
Interface between LVTTL and GTLP logic levels
s
Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
s
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
s
Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s
TTL compatible driver and control inputs
s
Designed using Fairchild advanced BiCMOS technology
s
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s
Power up/down and power off high impedance for live
insertion
s
Open drain on GTLP to support wired-or connection
s
A Port source/sink
−
24mA/
+
24mA
s
B Port sink
+
50mA
s
1:6 fanout clock driver for TTL port
s
1:2 fanout clock driver for GTLP port
s
Low voltage version of GTLP6C816
Ordering Code:
Order Number
GTLP6C816AMTC
Package Number
MTC24
Package Description
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device is also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pin Descriptions
Pin Names
Description
TTLIN, GTLPIN Clock Inputs
(LVTTL and GTLP respectively)
OEB
OEA
V
CCT
.GNDT
V
CC
GNDG
V
REF
OA0–OA5
OB0–OB1
Output Enable (Active LOW)
GTLP Port (LVTTL Levels)
Output Enable (Active LOW)
TTL Port (LVTTL Levels)
TTL Output Supplies
Internal Circuitry V
CC
OBn GTLP Output Grounds
Voltage Reference Input
TTL Buffered Clock Outputs
GTLP Buffered Clock Outputs
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS500179
www.fairchildsemi.com
GTLP6C816A
Functional Description
The GTLP6C816A is a clock driver providing LVTTL-to-GTLP clock translation, and GTLP-to-LVTTL clock translation in the
same package. The LVTTL-to-GTLP direction is a 1:2 clock driver path with a single Enable pin (OEB). For the
GTLP-to-LVTTL direction the clock receiver path is a 1:6 buffer with a single Enable control (OEA). Data polarity is inverting
for both directions.
Truth Tables
Inputs
TTLIN
H
L
X
Inputs
GTLPIN
H
L
X
OEA
L
L
H
OEB
L
L
H
Outputs
OBn
L
H
High Z
Outputs
OAn
L
H
High Z
Logic Diagram
www.fairchildsemi.com
2
GTLP6C816A
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
DC Output Voltage (V
O
)
Outputs 3-STATE
Outputs Active (Note 2)
DC Output Sink Current into
OA Port I
OL
DC Output Source Current
from OA Port I
OH
DC Output Sink Current into
OB Port in the LOW State I
OL
DC Input Diode Current (I
IK
)
V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
V
O
>
V
CC
ESD Rating
Storage Temperature (T
STG
)
100 mA
48 mA
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
Recommended Operating
Conditions
(Note 3)
Supply Voltage V
CC
Bus Termination Voltage (V
TT
)
GTLP
GTL
V
REF
Input Voltage (V
I
) on INA-Port
and Control Pins
0.0V to 3.45V
HIGH Level Output Current (I
OH
)
OA Port
LOW Level Output Current (I
OL
)
OA Port
1.47V to 1.53V
1.14V to 1.26V
0.98V to 1.02V
3.15V to 3.45V
−
48 mA
−
24 mA
+
24 mA
+
50 mA
−
40
°
C to
+
85
°
C
−
50 mA
−
50 mA
+
50 mA
>
2000V
−
65
°
C to
+
150
°
C
OB Port
Operating Temperature (T
A
)
Note 1:
Absolute Maximum continuous ratings are those values beyond
which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute maximum rated conditions is not
implied.
Note 2:
I
o
Absolute Maximum Rating must be observed.
Note 3:
Unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, V
REF
=
1.0V (unless otherwise noted).
Symbol
V
IH
V
IL
GTLPIN
Others
GTLPIN
Others
V
REF
(Note 5) GTLP
V
TT
(Note 5)
V
IK
V
OH
OAn Port
GTLP
V
CC
=
3.15V
V
CC
=
3.15V
I
I
= −18
mA
I
OH
= −100 µA
I
OH
= −18
mA
I
OH
= −24
mA
V
OL
OAn Port
V
CC
=
3.15V
I
OL
=
100
µA
I
OL
=
18 mA
I
OL
=
24 mA
V
OL
OBn Port
V
CC
=
3.15V
I
OL
=
100
µA
I
OL
=
40 mA
I
OL
=
50 mA
I
I
TTLIN/
Control Pins
GTLPIN
I
OFF
TTLIN
GTLPIN
I
PU/PD
I
OZH
I
OZL
I
CC
OAn or OBn Ports
OAn-Port
OBn-Port
OAn-Port
OAn or
OBn Ports
V
I
=
V
CC
or GND
V
CC
=
3.45V
V
CC
=
3.45V
V
CC
=
3.45V
V
CC
=
0
V
CC
=
0
V
CC
=
0 to 1.5V
V
CC
=
3.45V
V
CC
=
3.45V
V
I
=
3.45V
V
I
=
0V
V
I
=
V
TT
V
I
=
0
V
I
or V
O
=
0V to 3.45V
V
I
or V
O
=
0V to V
TT
OE
=
Don’t Care
V
O
=3.45V
V
O
=
1.5V
V
O
=
0
Outputs HIGH
Outputs LOW
Outputs Disabled
5.5
5
5.5
V
CC
−0.2
2.4
2.2
0.2
0.4
0.5
0.2
0.4
0.55
5
−5
5
−5
30
30
30
5
5
−5
10
10
10
mA
µA
µA
µA
µA
µA
µA
µA
V
V
V
1.0
1.5
−1.2
Test Conditions
Min
V
REF
+0.05
2.0
0.0
V
REF
−0.05
0.8
Typ
(Note 4)
V
TT
Max
Units
V
V
V
V
V
V
V
3
www.fairchildsemi.com
GTLP6C816A
DC Electrical Characteristics
Symbol
∆I
CC
C
I
C
O
TTLIN
Control Pins/GTLPIN/TTLIN
OAn Port
OBn Port
Note 4:
All typical values are at V
CC
=
3.3V and T
A
=
25°C.
(Continued)
Min
Typ
(Note 4)
2
4.5
6.0
8.0
pF
Max
Test Conditions
V
CC
=
3.45V
V
I
=
V
CC
−0.6
V
I
=
V
CC
or 0
V
I
=
V
CC
or 0
V
I
=
V
CC
or 0
Units
mA
Note 5:
GTLP V
REF
and V
TT
are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy.
In addition, V
TT
and R
TERM
can be adjusted to accommodate backplane impedances other than 50Ω, within the boundaries of not exceeding the DC Abso-
lute I
OL
ratings. Similarly V
REF
can be adjusted to compensate for changes in V
TT
.
AC Electrical Characteristics
Over recommended range of supply voltage and operating free air temperature. V
REF
=
1.0V (unless otherwise noted).
C
L
= 30 pF for OBn-Port and C
L
= 50 pF for OAn-Port.
From
Symbol
(Input)
f
TOGGLE
TTLIN
GTLPIN
t
PLH
t
PHL
t
PLH
t
PHL
t
RISE
t
FALL
t
RISE
t
FALL
t
PZH
, t
PZL
t
PLZ
, t
PHZ
t
PLH
t
PHL
Note 6:
All typical values are at V
CC
=
3.3 V and T
A
=
25°C.
To
(Output)
OBn
OAn
OBn
Min
Typ
(Note 6)
Max
Units
175
175
1.3
0.9
2.3
2.6
2.6
2.5
1.3
1.3
1.2
2.0
0.5
0.5
2.9
2.4
3.6
3.5
4.8
4.0
MHz
TTLIN
ns
4.3
4.1
ns
1.2
Transition Time, OB Outputs (20% to 80%)
Transition Time, OB outputs (20% to 80%)
Transition Time, OA outputs (10% to 90%)
Transition Time, OA outputs (10% to 90%)
OEA
OAn
4.1
ns
OEB
OBn
1.5
ns
ns
4.4
5.7
ns
2.1
5.3
GTLPIN
OAn
1.9
www.fairchildsemi.com
4
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