CY7C138, CY7C139
4K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
Features
■
■
■
■
■
■
■
Functional Description
The CY7C138 and CY7C139 are high speed CMOS 4K x 8 and
4K x 9 dual-port static RAMs. Various arbitration schemes are
included on the CY7C138/9 to handle situations when multiple
processors access the same piece of data. Two ports are
provided permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C138/9 can
be used as a standalone 8/9-bit dual-port static RAM or multiple
devices can be combined to function as a 16/18-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 16/18-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multipro-
cessor designs, communications status buffering, and dual-port
video/graphics memory.
Each port has independent control pins: chip enable (CE), read
or write enable (R/W), and output enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a chip enable (CE) pin or SEM pin.
True Dual-Ported Memory Cells that Enable Simultaneous
Reads of the Same Memory Location
4K x 8 Organization (CY7C138)
4K x 9 Organization (CY7C139)
0.65-micron CMOS for Optimum Speed and Power
High Speed Access: 15 ns
Low Operating Power: I
CC
= 160 mA (max.)
Fully Asynchronous Operation
■
Automatic Power Down
■
■
TTL Compatible
Expandable Data Bus to 32/36 Bits or more using
Master/Slave Chip Select when using more than one
Device
■
On-Chip Arbitration Logic
Semaphores Included to Permit Software Handshaking
between Ports
■
INT Flag for Port-to-Port Communication
■
Available in 68-pin PLCC
■
Pb-free Packages Available
■
Logic Block Diagram
R/W
L
CE
L
OE
L
R/W
R
CE
R
OE
R
(7C139)I/O
8L
I/O
7L
I/O
0L
BUSY
L
[1, 2]
A
11L
A
0L
ADDRESS
DECODER
I/O
CONTROL
I/O
CONTROL
I/O
8R
(7C139)
I/O
7R
I/O
0R
BUSY
R
A
11R
A
0R
[1, 2]
MEMORY
ARRAY
ADDRESS
DECODER
CE
L
OE
L
R/W
L
SEM
L
INT
L
[2]
\
INTERRUPT
SEMAPHORE
ARBITRATION
CE
R
OE
R
R/W
R
SEM
R
INT
R
[2]
M/S
Notes
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
Document #: 38-06037 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 03, 2009
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CY7C138, CY7C139
Pin Configurations
Figure 1. 68-Pin PLCC (Top View)
NC
[4]
OE L
R/W L
SEM
L
CEL
I/O 1L
I/O 0L
NC
NC
VCC
NC
A
11L
A
10L
A9L
9 8 7 6
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
5 4 3 2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
CY7C138/9
52
51
50
49
48
47
46
45
44
A8L
A7L
A6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
NC
[3]
OE
R
A
9R
A8R
R/W
R
SEM
R
CER
NC
NC
GND
NC
A
11R
A10R
A7R
A6R
I/O7R
Table 1. Pin Definitions
Left Port
I/O
0L–7L(8L)
A
0L–11L
CE
L
OE
L
R/W
L
SEM
L
Right Port
I/O
0R–7R(8R)
A
0R–11R
CE
R
OE
R
R/W
R
SEM
R
Description
Data Bus Input/Output
Address Lines
Chip Enable
Output Enable
Read/Write Enable
Semaphore Enable. When asserted LOW, allows access to eight semaphores. The
three least significant bits of the address lines will determine which semaphore to
write or read. The I/O
0
pin is used when writing to a semaphore. Semaphores are
requested by writing a 0 into the respective location.
Interrupt Flag. INT
L
is set when right port writes location FFE and is cleared when
left port reads location FFE. INT
R
is set when left port writes location FFF and is
cleared when right port reads location FFF.
Busy Flag
Master or Slave Select
Power
Ground
INT
L
BUSY
L
M/S
V
CC
GND
INT
R
BUSY
R
Table 2. Selection Guide
Description
Maximum Access Time (ns)
Maximum Operating Current
Maximum Standby Current for I
SB1
Notes
3. I/O
8R
on the CY7C139.
4. I/O
8L
on the CY7C139.
Commercial
Commercial
7C138-15
7C139-15
15
220
60
7C138-25
7C139-25
25
180
40
A5R
7C138-35
7C139-35
35
160
30
7C138-55
7C139-55
55
160
30
Unit
ns
mA
mA
Document #: 38-06037 Rev. *E
Page 2 of 17
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CY7C138, CY7C139
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
[5]
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ................................................–0.5V to +7.0V
DC Input Voltage
[6]
.........................................–0.5V to +7.0V
Output Current into Outputs (LOW) ............................. 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch Up Current .................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
5V ± 10%
5V ± 10%
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
GND < V
I
< V
CC
Output Disabled, GND < V
O
< V
CC
V
CC
= Max.,
I
OUT
= 0 mA,
Outputs Disabled
CE
L
and CE
R
> V
IH
,
f = f
MAX[7]
CE
L
and CE
R
> V
IH
,
f = f
MAX[7]
Both Ports
CE and CE
R
> V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V
or V
IN
< 0.2V, f = 0
[7]
One Port
CE
L
or CE
R
> V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or
V
IN
< 0.2V, Active
Port Outputs, f = f
MAX[7]
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
125
15
130
60
–10
–10
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 4.0 mA
2.2
0.8
+10
+10
220
–10
–10
7C138-15
7C139-15
Min
2.4
0.4
2.2
0.8
+10
+10
180
190
40
50
110
120
15
30
100
115
mA
mA
mA
mA
Max
7C138-25
7C139-25
Min
2.4
0.4
Max
V
V
V
V
μA
μA
mA
Unit
I
SB1
I
SB2
I
SB3
Standby Current
(Both Ports TTL Levels)
Standby Current
(One Port TTL Level)
Standby Current
(Both Ports CMOS Levels)
I
SB4
Standby Current
(One Port CMOS Level)
Notes
5. The Voltage on any input or I/O pin cannot exceed the power pin during power up.
6. Pulse width < 20 ns.
7. f
MAX
= 1/t
RC
= All inputs cycling at f = 1/t
RC
(except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby I
SB3
Document #: 38-06037 Rev. *E
Page 3 of 17
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CY7C138, CY7C139
Figure 2. AC Test Loads and Waveforms
5V
R1 = 893Ω
OUTPUT
C = 30 pF
R2 = 347Ω
OUTPUT
C = 30pF
V
TH
= 1.4V
(a) Normal Load (Load 1)
(b) Thévenin Equivalent Load 1)
(
ALL INPUT PULSES
OUTPUT
C = 30 pF
3.0V
GND
10%
90%
90%
10%
< 3 ns
(c) Three-State Delay (Load 3)
5V
R1 = 893Ω
OUTPUT
C = 5 pF
R2 = 347Ω
R
TH
= 250Ω
< 3 ns
Load (Load 2)
Switching Characteristics
Over the Operating Range
[9]
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
3
10
3
10
0
15
15
12
12
2
0
12
10
0
25
20
20
2
0
20
15
0
0
25
35
30
30
2
0
25
15
0
3
15
0
35
55
40
40
2
0
30
20
0
3
15
10
3
15
3
20
0
55
15
15
3
25
15
3
20
3
25
25
25
3
35
20
3
25
35
35
3
55
25
55
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
7C138-15
7C139-15
Min
Max
7C138-25
7C139-25
Min
Max
7C138-35
7C139-35
Min
Max
7C138-55
7C139-55
Min
Max
Unit
t
LZOE[10,11,12]
OE Low to Low Z
t
HZOE[10,11,12]
OE HIGH to High Z
t
LZCE[10,11,12]
CE LOW to Low Z
t
HZCE[10,11,12]
t
PU[12]
t
PD[12]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power Down
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold From Write End
Address Setup to Write Start
Write Pulse Width
Data Setup to Write End
Data Hold From Write End
WRITE CYCLE
Note
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06037 Rev. *E
Page 5 of 17
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