Final Electrical Specifications
LTC1096L/LTC1098L
Low Voltage, Micropower
Sampling 8-Bit Serial I/O
A/D Converters
December 1995
FEATURES
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s
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DESCRIPTIO
Specified at 2.65V Minimum Supply
Maximum Supply Current: 80µA
Auto Shutdown to 1nA
8-Pin SO Package
On-Chip Sample-and-Hold
Conversion Time: 32µs
Sample Rates: 16.5ksps
I/O Compatible with SPI, MICROWIRE
TM
, etc.
APPLICATI
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The LTC
®
1096L/LTC1098L are 3V micropower, 8-bit suc-
cessive approximation sampling A/D converters. They
typically draw only 40µA of supply current when convert-
ing and automatically power down to a typical supply
current of 1nA between conversions. They are packaged in
8-pin SO packages and operate on a 3V supply. These 8-
bit, switched capacitor, successive approximation ADCs
include a sample-and-hold. The LTC1096L has a single
differential analog input. The LTC1098L offers a software
selectable 2-channel multiplexed input.
On-chip serial ports allow efficient data transfer to a wide
range of microprocessors and microcontrollers over three
wires. This, coupled with micropower consumption, makes
remote location possible and facilitates transmitting data
through isolation barriers.
The circuits can be used in ratiometric applications or with
an external reference. The high impedance analog inputs
and the ability to operate with reduced spans (to 1V full
scale) allow direct connection to sensors and transducers
in many applications, eliminating the need for gain stages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a registered trademark of National Semiconductor Corporation.
Battery-Operated Systems
Remote Data Acquisition
Isolated Data Acquisition
Battery Monitoring
Temperature Measurement
TYPICAL APPLICATI
10µW, SO-8 Package, 8-Bit A/D Converter
Samples at 200Hz and Runs Off a 3V Battery
1µF
3V
1000
SUPPLY CURRENT, I
CC
(µA)
100
ANALOG INPUT
0V TO 3V RANGE
1 CS/
V
CC
SHDN
2
+IN
CLK
LTC1096L
3
–IN
D
OUT
4
GND
V
REF
8
7
6
5
SERIAL DATA LINK
MPU
SERIAL DATA LINK
(MICROWIRE AND
SPI COMPATIBLE)
10
1096/8 TA01
1
0.1
1
10
SAMPLE FREQUENCY (kHz)
100
1096/8 TA02
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
Supply Current vs Sample Rate
UO
UO
1
LTC1096L/LTC1098L
ABSOLUTE
AXI U
RATI GS
U
W W
W
(Notes 1 and 2)
Supply Voltage (V
CC
) to GND ................................... 12V
Voltage
Analog and Reference ................ –0.3V to V
CC
+ 0.3V
Digital Inputs......................................... –0.3V to 12V
Digital Outputs ........................... –0.3V to V
CC
+ 0.3V
Power Dissipation.............................................. 500mW
Operating Temperature
LTC1096LAC/LTC1098LAC .................... 0°C to 70°C
LTC1096LAI/LTC1098LAI .................. – 40°C to 85°C
LTC1096LC/LTC1098LC......................... 0°C to 70°C
LTC1096LI/LTC1098LI ....................... – 40°C to 85°C
Storage Temperature Range ................. – 65°c to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
PACKAGE/ORDER I FOR ATIO
TOP VIEW
CS/
1
SHDN
+IN 2
–IN 3
GND 4
8 V
CC
7 CLK
6 D
OUT
5 V
REF
ORDER PART
NUMBER
LTC1096LACS8
LTC1096LAIS8
LTC1096LCS8
LTC1096LIS8
S8 PART MARKING
096LIA
1096LA
1096LI
1096L
TOP VIEW
CS/
1
SHDN
CH0 2
CH1 3
GND 4
8 V
CC
(V
REF)
7 CLK
6 D
OUT
5 D
IN
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 150°C,
θ
JA
= 175°C/W
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 150°C,
θ
JA
= 175°C/W
Consult factory for Military grade parts.
RECO
SYMBOL
V
CC
f
CLK
t
CYC
t
hDI
t
suCS
t
WAKEUP
E DED OPERATI G CO DITIO S
CONDITIONS
V
CC
= 2.65V
LTC1096L, f
CLK
= 250kHz
LTC1098L, f
CLK
= 250kHz
V
CC
= 2.65V
V
CC
= 2.65V, LTC1096L
V
CC
= 2.65V, LTC1098L
V
CC
= 2.65V, LTC1096L
V
CC
= 2.65V, LTC1098L
V
CC
= 2.65V
V
CC
= 2.65V
V
CC
= 2.65V
V
CC
= 2.65V
LTC1096L, f
CLK
= 250kHz
LTC1098L, f
CLK
= 250kHz
MIN
2.65
25
58
58
450
1
1
10
10
1
1.6
1.6
2
56
56
TYP
MAX
4.0
250
UNITS
V
kHz
µs
µs
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
PARAMETER
Supply Voltage
Clock Frequency
Total Cycle Time
Hold Time, D
IN
After CLK↑
Setup Time CS↓ Before First CLK↑ (See Operating Sequence)
Wakeup Time CS↓ Before First CLK↓ After First CLK↑
(See Figure 1, LTC1096L Operating Sequence)
Wakeup Time CS↓ Before MSBF Bit CLK↓
(See Figure 2, LTC1098L Operating Sequence)
t
suDI
t
WHCLK
t
WLCLK
t
WHCS
t
WLCS
Setup Time, D
IN
Stable Before CLK↑
CLK High Time
CLK Low Time
CS High Time Between Data Transfer Cycles
CS Low Time During Data Transfer
2
U
U
U
U
W
U
(Note 3)
ORDER PART
NUMBER
LTC1098LACS8
LTC1098LAIS8
LTC1098LCS8
LTC1098LIS8
S8 PART MARKING
098LIA
1098LA
1098LI
1098L
U WW
LTC1096L/LTC1098L
CO VERTER A D
PARAMETER
Resolution (No Missing Code)
Offset Error
Linearity Error
Full Scale Error
Total Unadjusted Error (Note 5)
Analog Input Range
REF Input Range (Note 6)
Analog Input Leakage Current
V
CC
= 2.65V, V
REF
= 2.5V, f
CLK
= 250kHz, unless otherwise noted.
CONDITIONS
q
DIGITAL A D DC ELECTRICAL CHARACTERISTICS
V
CC
= 2.65V, V
REF
= 2.5V, f
CLK
= 250kHz, unless otherwise noted.
SYMBOL
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OZ
I
SOURCE
I
SINK
I
REF
PARAMETER
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage
Output Source Current
Output Sink Current
Reference Current
CONDITIONS
V
CC
= 3.6V
V
CC
= 2.65V
V
IN
= V
CC
V
IN
= 0V
V
CC
= 2.65V, I
O
= 10µA
I
O
= 360µA
V
CC
= 2.65V, I
O
= 400µA
CS =High
V
OUT
= 0V
V
OUT
= V
CC
CS = V
CC
t
CYC
≥
200µs, f
CLK
≤
50kHz
t
CYC
= 58µs, f
CLK
= 250kHz
CS = V
CC
LTC1096L,
LTC1098L,
t
CYC
≥
200µs, f
CLK
≤
50kHz
t
CYC
= 58µs, f
CLK
= 250kHz
t
CYC
≥
200µs, f
CLK
≤
50kHz
t
CYC
= 58µs, f
CLK
= 250kHz
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
I
CC
Supply Current
W U
U
U
ULTIPLEXER CHARACTERISTICS
LTC1096LA/LTC1098LA
MIN
TYP
MAX
8
±0.5
±0.5
±0.5
±1
– 0.05V to V
CC
+ 0.05V
– 0.05V to V
CC
+ 0.05V
q
q
q
q
LTC1096L/LTC1098L
MIN
TYP
MAX
8
±1
±1
±1
±1.5
UNITS
Bits
LSB
LSB
LSB
LSB
V
V
(Note 4)
V
REF
= 2.5V
(Note 6)
2.65
≤
V
CC
≤
4.0V
(Note 7)
q
±1
±1
µA
MIN
1.9
TYP
MAX
0.45
2.5
– 2.5
UNITS
V
V
µA
µA
V
V
2.4
2.1
2.64
2.50
0.3
±3
– 10
15
0.001 2.5
3.500 7.5
35.00 50.0
0.001
40
120
44
155
±
3
80
180
88
230
V
µA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
3
LTC1096L/LTC1098L
AC CHARACTERISTICS
V
CC
= 2.65V, V
REF
= 2.5V, f
CLK
= 250kHz, unless otherwise noted.
SYMBOL
t
SMPL
f
SMPL(MAX)
t
CONV
t
dDO
t
dis
t
en
t
hDO
t
f
t
r
C
IN
PARAMETER
Analog Input Sample Time
Maximum Sampling Frequency
Conversion Time
Delay Time, CLK↓ to D
OUT
Data Valid
Delay Time, CS↑ to D
OUT
Hi-Z
Delay Time, CLK↓ to D
OUT
Enable
Time Output Data Remains Valid After CLK↓
D
OUT
Fall Time
D
OUT
Rise Time
Input Capacitance
See Operating Sequences
See Test Circuits
See Test Circuits
See Test Circuits
C
LOAD
= 100pF
See Test Circuits
See Test Circuits
Analog Inputs
Digital Input
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to GND.
Note 3:
This device is specified at 2.65V. Consult factory for 5V specified
devices.
Note 4:
Linearity error is specified between the actual end points of the
A/D transfer curve.
Note 5:
Total unadjusted error includes offset, full scale, linearity,
multiplexer and hold step errors.
On Channel
Off Channel
q
q
q
q
q
CONDITIONS
See Operating Sequences
q
MIN
16.5
TYP
1.5
8
500
220
160
400
70
50
25
5
5
MAX
UNITS
CLK Cycles
kHz
CLK Cycles
1000
800
480
250
200
ns
ns
ns
ns
ns
ns
pF
pF
pF
Note 6:
Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
below GND or one diode drop above V
CC
. This spec allows 50mV forward
bias of either diode for 2.65V
≤
V
CC
≤
3.6V. This means that as long as the
reference or analog input does not exceed the supply voltage by more than
50mV, the output code will be correct. To achieve an absolute 0V to 3V
input voltage range will therefore require a minimum supply voltage of
2.950V over initial tolerance, temperature variations and loading.
Note 7:
Channel leakage current is measured after the channel selection.
PI FU CTIO S
LTC1096L
CS/SHDN (Pin 1):
Chip Select Input. A logic low on this
input enables the LTC1096L. A logic high on this input
disables the LTC1096L and disconnects the power to the
LTC1096L.
IN
+
(Pin 2):
Analog Input. This input must be free of noise
with respect to GND.
IN
–
(Pin 3):
Analog Input. This input must be free of noise
with respect to GND.
GND (Pin 4):
Analog Ground. GND should be tied directly
to an analog ground plane.
V
REF
(Pin 5):
Reference Input. The reference input defines
the span of the A/D converter and must be kept free of
noise with respect to GND.
D
OUT
(Pin 6):
Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7):
Shift Clock. This clock synchronizes the serial
data transfer.
V
CC
(Pin 8):
Power Supply Voltage. This pin provides
power to the A/D converter. It must be free of noise and
ripple by bypassing directly to the analog ground plane.
4
U
U
U
LTC1098L
CS/SHDN (Pin 1):
Chip Select Input. A logic low on this
input enables the LTC1098L. A logic high on this input
disables the LTC1098L and disconnects the power to the
LTC1098L.
CHO (Pin 2):
Analog Input. This input must be free of noise
with respect to GND.
LTC1096L/LTC1098L
PI FU CTIO S
CH1 (Pin 3):
Analog Input. This input must be free of noise
with respect to GND.
GND (Pin 4):
Analog Ground. GND should be tied directly
to an analog ground plane.
D
IN
(Pin 5):
Digital Data Input. The multiplexer address is
shifted into this pin.
D
OUT
(Pin 6):
Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7):
Shift Clock. This clock synchronizes the serial
data transfer.
V
CC
(V
REF
) (Pin 8):
Power Supply Voltage. This pin pro-
vides power and defines the span of the A/D converter. It
must be free of noise and ripple by bypassing directly to
the analog ground plane
TEST CIRCUITS
Load Circuit for t
dDO
, t
r
and t
f
1.4V
V
OH
V
OL
t
r
LTC1096/98 • TC01
D
OUT
100pF
Load Circuit for t
dis
and t
en
CS
TEST POINT
D
OUT
WAVEFORM 1
(SEE NOTE 1)
t
dis
D
OUT
WAVEFORM 2
(SEE NOTE 2)
10%
D
OUT
100pF
t
dis
WAVEFORM 1
LTC1096/98 • TC03
U
3k
U
U
Voltage Waveforms for D
OUT
Rise and Fall Times, t
r
, t
f
3k
TEST POINT
D
OUT
t
f
LTC1096/98 • TC02
Voltage Waveforms for t
dis
V
IH
V
CC
t
dis
WAVEFORM 2, t
en
90%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
LTC1096/98 • TC04
Voltage Waveforms for D
OUT
Delay Time, t
dDO
CLK
V
IL
t
dDO
V
OH
D
OUT
V
OL
LTC1096/98 • TC05
5
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