LTC1163/LTC1165
Triple 1.8V to 6V High-Side
MOSFET Drivers
FEATURES
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s
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DESCRIPTIO
Operates from 1.8V to 6V
0.01µA Standby Current
95µA Operating Current per Channel at 3.3V
Fully Enhances N-Channel Switches
No External Charge Pump Components
Built-In Gate Voltage Clamps
Easily Protected Against Supply Transients
Controlled Switching ON and OFF Times
Compatible with 5V, 3V and Sub-3V Logic Families
Available in 8-Pin SOIC
The LTC1163/LTC1165 triple low voltage MOSFET drivers
make it possible to switch supply or ground referenced
loads through inexpensive, low R
DS(ON)
N-channel switches
from as little as a 1.8V supply. The LTC1165 has inverting
inputs and makes it possible to directly replace P-channel
MOSFET switches while maintaining system drive polar-
ity. The LTC1163 has noninverting inputs.
Micropower operation, with 0.01µA standby current and
95µA operating current, coupled with a power supply
range of 1.8V to 6V, make the LTC1163/LTC1165 ideally
suited for 2- to 4-cell battery-powered applications. The
LTC1163/LTC1165 are also well suited for sub-3V, 3.3V
and 5V nominal supply applications.
The LTC1163/LTC1165 internal charge pumps boost the
gate voltage 8V above a 3.3V rail, fully enhancing inexpen-
sive N-channels for high- or low-side switch applications.
The LTC1163/LTC1165 are available in both an 8-pin DIP
and an 8-pin SOIC.
APPLICATI
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S
PCMCIA Card 3.3V/5V Switch
2-Cell High-Side Load Switching
Boost Regulator Shutdown to Zero Standby Current
Replacing P-Channel Switches
Notebook Computer Power Management
Palmtop Computer Power Management
Portable Medical Equipment
Mixed 3.3V and 5V Supply Switching
TYPICAL APPLICATI
(1.8V TO 3V)
2-Cell Triple High-Side Switch
18
+
2-CELL
BATTERY
PACK
+
10µF
16
GATE OUTPUT VOLTAGE (V)
RFD14N05LSM
RFD14N05LSM
RFD14N05LSM
14
12
10
8
6
4
2
IN1
CONTROL
LOGIC
OR
µP
V
S
OUT1
IN2 LTC1163 OUT2
LTC1165
IN3
OUT3
GND
2-CELL
LOAD
2-CELL
LOAD
2-CELL
LOAD
LTC1163 HAS NONINVERTING INPUTS
LTC1165 HAS INVERTING INPUTS
LTC1163/65 • TA01
0
0
1
2
3
4
SUPPLY VOLTAGE (V)
5
6
U
MOSFET Switch Gate Voltage
LTC1163/65 • TA02
UO
UO
1
LTC1163/LTC1165
ABSOLUTE
AXI U
RATI GS
Operating Temperature Range
LTC1163C/LTC1165C ........................... 0°C to 70°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
Supply Voltage ......................................................... 7V
Any Input Voltage .......................... 7V to (GND – 0.3V)
Any Output Voltage ....................... 20V to (GND – 0.3V)
Current (Any Pin)................................................. 50mA
PACKAGE/ORDER I FOR ATIO
TOP VIEW
IN1 1
IN2 2
IN3 3
GND 4
8
7
6
5
V
S
OUT1
OUT2
OUT3
ORDER PART
NUMBER
LTC1163CN8
LTC1165CN8
N8 PACKAGE
8-LEAD PLASTIC DIP
T
JMAX
= 100°C,
θ
JA
= 130°C/W
ELECTRICAL CHARACTERISTICS
SYMBOL
I
Q
PARAMETER
Quiescent Current OFF
CONDITIONS
V
S
= 1.8V to 6V, T
A
= 25°C, unless otherwise noted.
LTC1163C/LTC1165C
MIN
TYP
MAX
0.01
0.01
0.01
60
95
180
q
q
q
q
V
S
= 1.8V, V
IN1
= V
IN2
= V
IN3
= V
OFF
(Note 1,2)
V
S
= 3.3V, V
IN1
= V
IN2
= V
IN3
= V
OFF
(Note 1,2)
V
S
= 5V, V
IN1
= V
IN2
= V
IN3
= V
OFF
(Note 1,2)
V
S
= 1.8V, V
IN
= V
ON
(Note 2,3)
V
S
= 3.3V, V
IN
= V
ON
(Note 2,3)
V
S
= 5V, V
IN
= V
ON
(Note 2,3)
1.8V < V
S
< 2.7V
2.7V < V
S
< 6V
1.8V < V
S
< 6V
0V
≤
V
IN
≤
V
S
V
S
= 1.8V, V
IN
= V
ON
(Note 2)
V
S
= 2V, V
IN
= V
ON
(Note 2)
V
S
= 2.2V, V
IN
= V
ON
(Note 2)
V
S
= 3.3V, V
IN
= V
ON
(Note 2)
V
S
= 5V, V
IN
= V
ON
(Note 2)
V
S
= 3.3V, C
GATE
= 1000pF
Time for V
GATE
> V
S
+ 1V
Time for V
GATE
> V
S
+ 2V
V
S
= 5V, C
GATE
= 1000pF
Time for V
GATE
> V
S
+ 1V
Time for V
GATE
> V
S
+ 2V
80%
×
V
S
70%
×
V
S
Quiescent Current ON
V
INH
V
INL
I
IN
C
IN
V
GATE
– V
S
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
Gate Voltage Above Supply
t
ON
Turn-ON Time
2
U
U
W
W W
U
W
TOP VIEW
IN1 1
IN2 2
IN3 3
GND 4
8 V
S
7 OUT1
6 OUT2
5 OUT3
ORDER PART
NUMBER
LTC1163CS8
LTC1165CS8
S8 PART MARKING
1163
1165
S8 PACKAGE
8-LEAD PLASTIC SOIC
T
JMAX
= 100°C,
θ
JA
= 150°C/W
UNITS
µA
µA
µA
µA
µA
µA
V
V
1
1
1
120
200
400
15%
×
V
S
±1
5
3.5
4.0
4.5
6.0
5.0
40
60
30
40
4.1
4.6
5.2
8.0
9.0
120
180
95
130
6.0
7.0
8.0
9.5
13.0
400
600
300
400
V
µA
pF
V
V
V
V
V
µs
µs
µs
µs
q
q
q
q
q
LTC1163/LTC1165
ELECTRICAL CHARACTERISTICS
SYMBOL
t
OFF
PARAMETER
Turn-OFF Time
CONDITIONS
V
S
= 1.8V to 6V, T
A
= 25°C, unless otherwise noted.
LTC1163C/LTC1165C
MIN
TYP
MAX
20
15
65
45
200
150
UNITS
µs
µs
V
S
= 3.3V, C
GATE
= 1000pF
Time for V
GATE
< 0.5V
V
S
= 5V, C
GATE
= 1000pF
Time for V
GATE
< 0.5V
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1:
Quiescent current OFF is for all channels in OFF condition.
Note 2:
LTC1163: V
OFF
= 0V, V
ON
= V
S
. LTC1165: V
OFF
= V
S
, V
ON
= 0V
Note 3:
Quiescent current ON is per driver and is measured independently.
TYPICAL PERFOR A CE CHARACTERISTICS
Standby Supply Current
5
T
A
= 25°C
ALL THREE INPUTS = OFF
4
SUPPLY CURRENT (µA)
3
2
1
0
–1
SUPPLY CURRENT (µA)
500
400
300
200
100
0
600
T
A
= 25°C
ONE INPUT = ON
OTHER INPUTS = OFF
V
GATE
– V
S
(V)
0
1
2
3
4
SUPPLY VOLTAGE (V)
LTC1163/65 • TPC01
Input Threshold Voltage
6
T
A
= 25°C
INPUT THRESHOLD VOLTAGE (V)
5
4
3
V
HI
2
1
0
V
LO
TURN-ON TIME (µs)
500
400
300
200
100
0
600
TURN-OFF TIME (µs)
0
1
2
3
4
SUPPLY VOLTAGE (V)
LTC1163/65 •TPC04
U W
5
6
5
6
Supply Current per Driver ON
12
Gate Voltage Above Supply
T
A
= 25°C
10
8
6
4
2
0
0
1
2
3
4
SUPPLY VOLTAGE (V)
5
6
0
1
2
3
4
SUPPLY VOLTAGE (V)
5
6
LTC1163/65 • TPC02
LTC1163/65 • TPC03
Turn-ON Time
300
C
GATE
= 1000pF
250
200
150
100
50
0
Turn-OFF Time
C
GATE
= 1000pF
TIME FOR V
GATE
< 0.5V
V
GS
= 2V
V
GS
= 1V
0
1
2
3
4
SUPPLY VOLTAGE (V)
5
6
0
1
2
3
4
SUPPLY VOLTAGE (V)
5
6
LTC1163/65 • TPC05
LTC1163/65 • TA06
3
LTC1163/LTC1165
TYPICAL PERFOR A CE CHARACTERISTICS
Standby Supply Current
5
4
SUPPLY CURRENT (µA)
GATE DRIVE CURRENT (µA)
3
2
1
0
–1
SUPPLY CURRENT (µA)
0
10
50
20
30
40
TEMPERATURE (°C)
LTC1163/65 • TPC07
PI FU CTIO S
Input Pins
The LTC1163 is noninverting; i.e., the MOSFET gate is
driven above the supply when the input pin is held high.
The LTC1165 is inverting and drives the MOSFET gate high
when the input pin is held low. The inverting inputs of the
LTC1165 allow P-channel switches to be replaced by
lower resistance/cost N-channel switches while maintain-
ing system drive polarity.
The LTC1163/LTC1165 logic inputs are high impedance
CMOS gates with ESD protection diodes to ground and
therefore should not be forced below ground. The inputs
can however, be driven above the power supply rail as
there are no clamping diodes connected between the input
pins and supply pin. This facilitates operation in mixed
5V/3V systems.
Output Pins
The output pin is either driven to ground when the switch
is turned OFF or driven above the supply rail when the
switch is turned ON. The output is clamped to about 14V
above ground by a built-in Zener clamp. This pin has a
relatively high impedance when driven above the rail (the
equivalent of a few hundred kΩ). Care should be taken to
minimize any loading of this pin by parasitic resistance to
ground or supply.
Supply Pin
A 150Ω resistor should be inserted in series with the
ground pin or supply pin if negative supply voltage tran-
sients are anticipated. This will limit the current flowing
from the power source into the LTC1163/LTC1165 to tens
of milliamps during reverse battery conditions.
OPERATIO
The LTC1163/LTC1165 are triple micropower MOSFET
drivers designed for operation over the 1.8V to 6V supply
range and include the following functional blocks:
3V Logic Compatible Inputs
The LTC1163/LTC1165 inputs have been designed to
accommodate a wide range of 3V and 5V logic families.
4
U W
60
70
Supply Current per Driver ON
300
250
MOSFET Gate Drive Current
1000
T
A
= 25°C
100
V
S
= 5V
10
V
S
= 3.3V
1
V
S
= 1.8V
V
S
= 2.2V
10
200
V
S
= 5V
150
100
50
0
V
S
= 3.3V
V
S
= 1.8V
0
10
20
30
40
50
TEMPERATURE (°C)
60
70
0.1
0
2
4
6
8
GATE VOLTAGE ABOVE SUPPLY (V)
LTC1163/65 • TPC08
LTC1163/65 • TPC09
U
U
U
U
The input threshold voltage is set at roughly 50% of the
supply voltage and approximately 200mV of input hyster-
esis is provided to ensure clean switching.
The input enables all of the following circuit blocks: the
bias generator, the high frequency oscillator and gate
charge pump. Therefore, when the input is turned off, the
entire circuit powers down and the supply current drops
below 1µA.
LTC1163/LTC1165
OPERATIO
Gate Charge Pump
Gate drive for the power MOSFET is produced by an
internal charge pump circuit which generates a gate volt-
age substantially higher than the power supply voltage.
The charge pump capacitors are included on chip and
therefore no external components are required to generate
gate drive.
BLOCK DIAGRA
APPLICATIO S I FOR ATIO
Logic-Level MOSFET Switches
The LTC1163/LTC1165 are designed to operate with
logic-level N-channel MOSFET switches. Although there
is some variation among manufacturers, logic-level
MOSFET switches are typically rated with V
GS
= 4V with
a maximum continuous V
GS
rating of
±10V.
R
DS(ON)
and
maximum V
DS
ratings are similar to standard MOSFETs
and there is generally little price differential. Logic-level
MOSFETs are frequently designated by an “L” and are
usually available in surface mount packaging. Some
logic-level MOSFETs are rated with V
GS
up to
±15V
and
can be used in applications which require operation over
the entire 1.8V to 6V range.
Powering Large Capacitive Loads
Electrical subsystems in portable battery-powered equip-
ment are typically bypassed with large filter capacitors to
reduce supply transients and supply induced glitching. If
not properly powered however, these capacitors may
themselves become the source of supply glitching.
U
W
W
U U
U
Controlled Gate Rise and Fall Times
When the input is switched ON and OFF, the gate is
charged by the internal charge pump and discharged in a
controlled manner. The charge and discharge rates have
been set to minimize RFI and EMI emissions.
(One Channel)
LTC1165
HIGH
FREQUENCY
OSCILLATOR
CHARGE
PUMP
GATE
LTC1163
INPUT
BIAS
GENERATOR
GATE
DISCHARGE
LOGIC
14V
LTC1163/65 • BD
For example, if a 100µF capacitor is powered through a
switch with a slew rate of 0.1V/µs, the current during start-
up is:
I
START
= C(∆V/∆t)
= (100
×
10
– 6
)(1
×
10
5
)
= 10A
Obviously, this is too much current for the regulator (or
output capacitor) to supply and the output will glitch by as
much as a few volts.
The startup current can be substantially reduced by limit-
ing the slew rate at the gate of an N-channel as shown in
Figure 1. The gate drive output of the LTC1163/LTC1165
is passed through a simple RC network, R1 and C1, which
substantially slows the slew rate of the MOSFET gate to
approximately 1.5
×
10
– 4
V/µs. Since the MOSFET is
operating as a source follower, the slew rate at the source
is essentially the same as that at the gate, reducing the
startup current to approximately 15mA which is easily
5
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