CY7C1360A
CY7C1362A
256K x 36/512K x 18 Synchronous
Pipelined Burst SRAM
Features
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Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
Fast clock speed: 225, 200, 166, and 150 MHz
Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
3.3V –5% and +10% power supply
3.3V or 2.5V I/O supply
5V-tolerant inputs except I/Os
Clamp diodes to V
SS
at all inputs and outputs
Common data inputs and data outputs
Byte Write Enable and Global Write control
Multiple chip enables for depth expansion:
three chip enables for A package version and two chip
enables for BG and AJ package versions
Address pipeline capability
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst
sequence)
Automatic power-down feature available using ZZ
mode or CE deselect
JTAG boundary scan for BG and AJ package version
Low-profile 119-bump, 14-mm × 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), depth-expansion
Chip Enables (CE
2
and CE
3
), burst control inputs (ADSC,
ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and
BWE), and global Write (GW). However, the CE
3
chip enable
input is only available for the TA package version.
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data outputs (Q), enabled by
OE, are also asynchronous.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
Address, data inputs, and Write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the Write control inputs.
Individual byte Write allows individual byte to be written. BWa
controls DQa. BWb controls DQb. BWc controls DQc. BWd
controls DQd. BWa, BWb, BWc, and BWd can be active only
with BWE being LOW. GW being LOW causes all bytes to be
written. The x18 version only has 18 data inputs/outputs (DQa
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and
DQd).
For the BGA and TQFP AJ package versions, four pins are
used to implement JTAG test capabilities: Test Mode Select
(TMS), Test Data-In (TDI), Test Clock (TCK), and Test
Data-Out (TDO). The JTAG circuitry is used to serially shift
data to and from the device. JTAG inputs use LVTTL/LVCMOS
levels to shift data during this testing mode of operation. The
TA package version does not offer the JTAG capability.
The CY7C1360A and CY7C1362A operate from a +3.3V
power supply. All inputs and outputs are LVTTL-compatible.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1360A and CY7C1362A SRAMs integrate 262,144
× 36 and 524,288 × 18 SRAM cells with advanced
Selection Guide
7C1360A-225
7C1362A-225
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
2.5
650
10
7C1360A-200
7C1362A-200
3.0
600
10
7C1360A-166
7C1362A-166
3.5
520
10
7C1360A-150
7C1362A-150
3.5
460
10
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document #: 38-05258 Rev. *C
•
3901 North First Street
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San Jose
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CA 95134 • 408-943-2600
Revised January 18, 2003
CY7C1360A
CY7C1362A
256K × 36 Pin Descriptions
X36 PBGA Pins
4P
4N
2A, 3A, 5A, 6A, 3B, 5B,
6B, 2C, 3C, 5C, 6C,
2R, 6R, 3T, 4T, 5T
X36 QFP Pins
Name
Type
Input-
Synchronous
Description
Addresses:
These inputs are registered and must meet
the set-up and hold times around the rising edge of CLK.
The burst counter generates internal addresses
associated with A0 and A1, during burst cycle and wait
cycle.
37
A0
36
A1
35, 34, 33, 32, 100, A
99, 82, 81, 44, 45,
46, 47, 48, 49, 50
92 (AJ Version)
43 (A Version)
93
94
95
96
87
BWa
BWb
BWc
BWd
BWE
5L
5G
3G
3L
4M
Input-
Synchronous
Byte Write:
A byte Write is LOW for a Write cycle and
HIGH for a Read cycle. BWa controls DQa. BWb controls
DQb. BWc controls DQc. BWd controls DQd. Data I/O are
high impedance if either of these inputs are LOW, condi-
tioned by BWE being LOW.
Write Enable:
This active LOW input gates byte Write
operations and must meet the set-up and hold times
around the rising edge of CLK.
Global Write:
This active LOW input allows a full 36-bit
Write to occur independent of the BWE and BWn lines
and must meet the set-up and hold times around the rising
edge of CLK.
Clock:
This signal registers the addresses, data, chip
enables, Write control, and burst control inputs on its
rising edge. All synchronous inputs must meet set-up and
hold times around the clock’s rising edge.
Chip Enable:
This active LOW input is used to enable the
device and to gate ADSP.
Chip Enable:
This active HIGH input is used to enable
the device.
Chip Enable:
This active LOW input is used to enable the
device. Not available for BG and AJ package versions.
Output Enable:
This active LOW asynchronous input
enables the data output drivers.
Address Advance:
This active LOW input is used to
control the internal burst counter. A HIGH on this pin
generates wait cycle (no address advance).
Address Status Processor:
This active LOW input,
along with CE being LOW, causes a new external address
to be registered and a Read cycle is initiated using the
new address.
Address Status Controller:
This active LOW input
causes the device to be deselected or selected along with
new external address to be registered. A Read or Write
cycle is initiated depending upon Write control inputs.
Mode:
This input selects the burst sequence. A LOW on
this pin selects Linear Burst. A NC or HIGH on this pin
selects Interleaved Burst.
Input-
Synchronous
Input-
Synchronous
4H
88
GW
4K
89
CLK
Input-
Synchronous
4E
2B
–
(not available for
PBGA)
4F
4G
98
97
CE
CE
2
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input
Input-
Synchronous
Input-
Synchronous
92
CE
3
(for A version only)
86
83
OE
ADV
4A
84
ADSP
4B
85
ADSC
Input-
Synchronous
3R
31
MODE
Input-
Static
7T
64
ZZ
Input-
Sleep:
This active HIGH input puts the device in low
Asynchronous power consumption standby mode. For normal operation,
this input has to be either LOW or NC (No Connect).
Document #: 38-05258 Rev. *C
Page 5 of 28
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