LTC1264
High Speed, Quad Universal
Filter Building Block
FEATURES
s
s
s
s
s
s
s
s
DESCRIPTIO
High Speed, Up to 250kHz Center Frequency
Four Identical Filters in a 0.3" Wide Package
Clock-to-Center Frequency Ratio of 20:1
Double-Sampling, Improved Aliasing
Operates from
±2.37V
to
±8V
Power Supplies
Customized Version with Internal Resistors Available
Low Noise
Low Harmonic Distortion
The LTC
®
1264 consists of four identical, high speed 2nd
order switched-capacitor filter building blocks designed
for center frequencies up to 250kHz. Each building block,
together with three to five resistors, can provide 2nd order
functions like lowpass, highpass, bandpass and notch.
The center frequency of each 2nd order section is tuned via
an external clock. The clock-to-center frequency ratio is
internally set to 20:1, but it can be modified via external
resistors.
The aliasing performance of the LTC1264 is improved by
double-sampling each 2nd order section. Input signal
frequencies can reach up to twice the clock frequency
before any alias products will be detectable.
For Q
≤
5 and for T
A
< 85°C, the maximum center
frequency is 160kHz. For Q
≤
2, the maximum center
frequency is 250kHz. Up to 8th order filters can be realized
by cascading all four 2nd order sections.
A customized monolithic version of the LTC1264 includ-
ing internal thin film resistors can be obtained.
APPLICATI
s
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s
s
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S
Digital Communications
Spread Spectrum Communications
Spectral Analysis
Loran Receivers
Instrumentation
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATI
50k
IN
10k
HPB/NB
50k
BPB
MAXIMUM POWER
f
CENTER
SUPPLY
160kHz
±7.5V
120kHz
±5V
60kHz
Single 5V
0.1µF
LPB
SB
AGND
V
+
SA
LPA
50k
BPA
10k
HPA/NA
INV A
50k
INV B
Clock-Tunable 8th Order Bandpass Filter, f
CENTER
= f
CLK
/20
50k
INV C
10k
HPC/NC
50k
BPC
LPC
LTC1264
SC
V
–
CLK
SD
LPD
BPD
HPD/ND
10k
INV D
50k
1264 TA01
Gain vs Frequency
100kHz Bandpass, f
–3dB
Bandwidth = f
CENTER
/10
10
0
–10
–20
GAIN (dB)
–30
–40
–50
f
CLK
0.1µF
OUT
50k
–60
–70
–80
10k
100k
FREQUENCY (Hz)
1M
1264 TA02
U
UO
UO
1
LTC1264
ABSOLUTE
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
INV B
HPB/NB
BPB
LPB
SB
AGND
V
+
SA
LPA
1
2
3
4
5
6
7
8
9
24 INV C
23 HPC/NC
22 BPC
21 LPC
20 SC
19 V
–
18 CLK
17 SD
16 LPD
15 BPD
14 HPD/ND
13 INV D
S PACKAGE
24-LEAD PLASTIC SOL
Total Supply Voltage (V
+
to V
–
) .............................. 16V
Input Voltage (Note 2) ........... (V
+
+ 0.3V) to (V
–
– 0.3V)
Output Short-Circuit Duration .......................... Indefinite
Power Dissipation............................................. 400mW
Burn-In Voltage ...................................................... 16V
Operating Temperature Range ............... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
LTC1264CN
LTC1264CS
BPA 10
HPA/NA 11
INV A 12
N PACKAGE
24-LEAD PLASTIC DIP
T
JMAX
= 110°C,
θ
JA
= 65°C/W (N)
T
JMAX
= 110°C,
θ
JA
= 85°C/W (S)
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
(Internal Op Amps) T
A
= 25°C, unless otherwise noted.
PARAMETER
Operating Supply Range
Voltage Swings
CONDITIONS
V
S
=
±2.375V,
R
L
= 5k
V
S
=
±5V,
R
L
= 5k
q
MIN
±2.375
±3.2
±3.1
TYP
±1.5
±3.7
±6
3
80
7
10
MAX
±8
V
S
=
±7.5,
R
L
= 5k
Output Short-Circuit Current (Source/Sink)
DC Open-Loop Gain
GBW Product
Slew Rate
UNITS
V
V
V
V
V
mA
dB
MHz
V/µs
(Complete Filter) V
S
=
±5V,
f
CLK
= 1MHz, all sides mode 1, f
O
= 50kHz, Q = 5, T
A
= 25°C, unless otherwise noted.
PARAMETER
Center Frequency Range, f
O
(Note 1)
CONDITIONS
V
S
=
±7.5V,
T
A
< 85°C, Q < 2
V
S
=
±5V,
T
A
< 85°C, Q < 2
V
S
=
±2.5V,
T
A
< 85°C, Q < 2
V
S
=
±7.5V
q
MIN
Clock-to-Center Frequency Ratio, f
CLK
/f
O
Center Frequency Error (Note 3)
TYP
0.1 - 250
0.1 - 200
0.1 - 100
20:1
±0.1
±0.2
MAX
UNITS
kHz
kHz
kHz
%
%
%
%
%
%
%
%
%
ppm/°C
ppm/°C
V
S
=
±5V
q
±
0.7
±0.8
±0.8
±1.0
0.8
1.0
7.0
Clock-to-Center Frequency Ratio,
Side-to-Side Matching
Q Accuracy
f
O
Temperature Coefficient
Q Temperature Coefficient
V
S
=
±2.375V
V
S
≥ ±5V
q
– 1.6
0.4
– 2.7
q
V
S
=
±5V
f
CLK
< 2MHz
f
CLK
< 2MHz
±1
5
2
U
W
U
U
W W
W
LTC1264
ELECTRICAL CHARACTERISTICS
(Complete Filter) V
S
=
±5V,
f
CLK
= 1MHz, all sides mode 1, f
O
= 50kHz, Q = 5, T
A
= 25°C, unless otherwise noted.
PARAMETER
DC Offset Voltage (Note 2)
CONDITIONS
V
OS1
(DC Offset of Input Inverter)
V
OS2
(DC Offset of First Integrator)
V
OS3
(DC Offset of Second Integrator)
V
S
=
±7.5V
(f
CLK
is a Square Wave)
V
S
=
±5V
(f
CLK
is a Square Wave)
V
S
=
±2.375V
(f
CLK
is a Square Wave)
V
S
=
±7.5V,
T
A
= 25°C
V
S
=
±5V
MIN
q
q
q
TYP
MAX
±20
±45
±45
Clock Feedthrough
Maximum Clock Frequency
Power Supply Current
9
q
160
120
90
6
14
23
26
UNITS
mV
mV
mV
µV
RMS
µV
RMS
µV
RMS
MHz
mA
mA
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1:
Please refer to Typical Maximum Q vs Clock Frequency graphs.
Note 2:
Calculations of output DC offsets of one 2nd order section. Also
see Block Diagram.
MODE
1
1b
2
3
V
OSN
PINS 2, 11, 14, 23
V
OS1
[(1Q) + 1
||H
OLP
||]
– V
OS3
/Q
V
OS1
[(1/Q) + 1 + R2/R1] – V
OS3
/Q
[V
OS1
(1 + R2/R1 + R2/R3 + R2/R4) – V
OS3
(R2/R3)]
• [R4/(R2 + R4)] + V
OS2
[R2/(R2 + R4)]
V
OS2
Note 3:
The center frequency f
O
, error is calculated as:
f
O
(measured) – f
O
(ideal)
• 100
f
O
(ideal)
V
OSBP
PINS 3, 10, 15, 22
V
OS3
V
OS3
V
OS3
V
OS3
V
OSN
– V
OS2
V
OSLP
PINS 4, 9, 16, 21
≈(V
OSN
– V
OS2
)(1 + R5/R6)
V
OSN
– V
OS2
V
OS1
[1 + R4/R1 + R4/R2 + R4/R3] – V
OS2
(R4/R2)
– V
OS3
(R4/R3)
TYPICAL PERFOR A CE CHARACTERISTICS
Typical Maximum Q
vs Clock Frequency
26
24
22
20
18
16
14
12
10
8
6
4
2
0
A
V
S
= ±7.5V
T
A
≤
85°C
26
24
22
20
18
16
14
12
10
8
6
4
2
0
TYPICAL MAXIMUM Q
TYPICAL MAXIMUM Q
TYPICAL MAXIMUM Q
A. MODES 1, 1b
B. MODES 3, 3a
B
1.5
2.0
2.5 3.0 3.5
4.0 4.5
CLOCK FREQUENCY (MHz)
U W
5.0
1264 G01
Typical Maximum Q
vs Clock Frequency
A
Typical Maximum Q
vs Clock Frequency
20
V
S
= ±5V
T
A
≤
85°C
A. MODES 1, 1b
B. MODES 3, 3a
A
18
16
14
12
10
8
6
4
2
B
V
S
= SINGLE 5V
T
A
≤
85°C
A. MODES 1, 1b
B. MODES 3, 3a
B
1.0
1.5
3.0
2.0
3.5
2.5
CLOCK FREQUENCY (MHz)
4.0
1264 G02
0
1.0
1.2
1.6
1.8
1.4
CLOCK FREQUENCY (MHz)
2.0
1264 G03
3
LTC1264
TYPICAL PERFOR A CE CHARACTERISTICS
Typical Bandpass Gain Error
vs Clock Frequency
5
TYPICAL BANDPASS GAIN ERROR (dB)
TYPICAL BANDPASS GAIN ERROR (dB)
4
4
TYPICAL BNADPASS GAIN ERROR (dB)
MODE 1
Q=2
T
A
= 25°C
3
V
S
= ±5V
2
V
S
= ±7.5V
1
0
2.0
2.4
3.2
3.6
2.8
CLOCK FREQUENCY (MHz)
Typical Bandpass Gain Error
vs Clock Frequency
5
TYPICAL BANDPASS GAIN ERROR (dB)
4
MODE 3
Q=4
T
A
= 25°C
V
S
= SINGLE 5V
f
CLK
/f
O
3
V
S
= ±7.5V
2
1
0
1
Noise vs R2/R4 Ratio
600
500
400
300
200
100
0
POWER SUPPLY CURRENT (mA)
NOISE (µV
RMS
)
0
0.2
4
U W
1264 G04
Typical Bandpass Gain Error
vs Clock Frequency
5
MODE 1
Q=4
T
A
= 25°C
V
S
= ±5V
3
5
Typical Bandpass Gain Error
vs Clock Frequency
MODE 1
V
S
= SINGLE 5V
TA = 25°C
4
3
Q=4
2
Q=2
1
2
V
S
= ±7.5V
1
4.0
0
2.0
2.4
3.2
3.6
2.8
CLOCK FREQUENCY (MHz)
4.0
1264 G05
0
1.3
1.4
1.7 1.8 1.9
1,5 1.6
CLOCK FREQUENCY (MHz)
2.0
1264 G06
Ratio (f
CLK
/f
O
) vs
Clock Frequency
20.5
20.4
20.3
20.2
20.1
20.0
19.9
19.8
19.7
19.6
Q=2
Q = 10
Q=4
BANDPASS OUT
MODE 1
V
S
= ±7.5V
V
S
= ±5V
2
3
4
1264 G15
19.5
1
2
3
4
1264 G11
CLOCK FREQUENCY (MHz)
CLOCK FREQUENCY (MHz)
Power Supply Current
vs Supply Voltage
48
MODE 3
V
S
= ±7.5V
Q=2
R2
f
f
O
=
CLK
20 R4
44
40
36
32
28
24
20
16
12
8
4
0
–55°C
25°C
125°C
√
0.4
0.6
0.8
RESISTOR RATIO (R2/R4)
1.0
1264 G12
0 2
4 6 8 10 12 14 16 18 20 22 24
POWER SUPPLY VOLTAGE (V
+
– V
–
)
1264 G14
LTC1264
PI FU CTIO S
V
+
, V
–
(Pins 7, 19):
Power Supply Pins. The V
+
(Pin 7) and
the V
–
(Pin 19) should each be bypassed with a 0.1µF
capacitor to an adequate analog ground. The filter’s power
supplies should be isolated from other digital or high
voltage analog supplies. A low noise linear supply is
recommended. Using a switching power supply will lower
the signal-to-noise ratio of the filter. The supply during
power-up should have a slew rate less than 1V/µs. When
V
+
is applied before V
–
and V
–
is allowed to go above
ground, a diode should clamp V
–
to prevent latch-up.
Figures 1 and 2 show typical connections for dual and
single supply operation.
AGND (Pin 6):
Analog Ground Pin. The filter performance
depends on the quality of the analog signal ground. For
either dual or single supply operation, an analog ground
plane surrounding the package is recommended. The
analog ground plane should be connected to any digital
ground at a single point. For dual supply operation, Pin 6
should be connected to the analog ground plane. For
single supply operation, Pin 6 should be biased at 1/2
supply and should be bypassed to the analog ground plane
with at least a 1µF capacitor (Figure 2). For single 5V
operation and f
CLK
greater than 1MHz, pin 6 should be
biased at 2V. This minimizes passband gain and phase
variations.
ANALOG
GROUND
PLANE
1
2
3
4
5
6
7.5V
0.1µF
7
8
9
10
11
12
STAR
SYSTEM
GROUND
*
OPTIONAL, 1N4148, 1N5819
Figure 1. Dual Supply Ground Plane Connections
U
U
U
24
23
22
–7.5V
21
20
19
LTC1264
18
17
16
15
14
13
ANALOG
GROUND
PLANE
1
2
3
24
23
22
21
20
*
19
LTC1264
18
17
*
16
15
14
13
*
0.1µF
4
V
+
5k
*
5
V
+
/2 6
+
1µF
5k
V
+
7
*
8
9
10
11
12
DIGITAL
GROUND
PLANE
200Ω
CLOCK
SOURCE
1264 F01
STAR
SYSTEM
GROUND
DIGITAL
GROUND
PLANE
200Ω
CLOCK
SOURCE
*
FOR MODE 3, THE S NODE PINS 5, 8,
17, 20 SHOULD BE TIED TO PIN 6
1264 F02
Figure 2. Single Supply Ground Plane Connections
5
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