written into the location specified on the address pins (A
0
through A
14
). If byte high enable (BHE) is LOW, then data from
I/O pins (I/O
9
through I/O
16
) is written into the location speci-
fied on the address pins (A
0
through A
14
).
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing the write
enable (WE) HIGH. If byte low enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O
1
to I/O
8
. If byte high enable (BHE) is LOW, then
data from memory will appear on I/O
9
to I/O
16
. See the truth
table at the back of this datasheet for a complete description
of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020V is available in standard 44-pin TSOP type II
and 400-mil-wide SOJ packages.
Functional Description
The CY7C1020V is a high-performance CMOS static RAM or-
ganized as 32,768 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking chip enable
(CE) and write enable (WE) inputs LOW. If byte low enable
Logic Block Diagram
DATA IN DRIVERS
Pin Configuration
SOJ / TSOP II
Top View
NC
A
14
A
13
A
12
A
11
CE
I/O
1
I/O
2
I/O
3
I/O
4
V
CC
V
SS
I/O
5
I/O
6
I/O
7
I/O
8
WE
A
10
A
9
A
8
A
7
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
6
A
5
A
4
A
3
A
2
A
1
A
0
32K x 16
RAM Array
I/O
1
– I/O
8
I/O
9
– I/O
16
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
0
A
1
A
2
OE
BHE
BLE
I/O
16
I/O
15
I/O
14
I/O
13
V
SS
V
CC
I/O
12
I/O
11
I/O
10
I/O
9
NC
A
3
A
4
A
5
A
6
NC
1021-2
Selection Guide
7C1020V-10
Maximum Access Time (ns)
Maximum Operating Current (mA)
L
Maximum CMOS Standby Current (mA)
L
Shaded areas contain advanced information
7C1020V-12
12
120
90
1
0.1
7C1020V-15
15
110
80
1
0.1
7C1020V-20
20
100
70
1
0.1
7C1020V-25
25
100
70
1
0.1
10
130
100
1
0.1
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
• CA 95134 •
408-943-2600
October 1996 – Revised January 10, 1997
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[1]
.... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
.....................................–0.5V to V
CC
+0.5V
DC Input Voltage
[1]
..................................–0.5V to V
CC
+0.5V
CY7C1020V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
[2]
0°C to +70°C
-40°C to +85°C
V
CC
3.0V - 3.6V
3.0V - 3.6V
Electrical Characteristics
Over the Operating Range
7C1020V-10
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
— TTL Inputs
Automatic CE
Power-Down Current
— CMOS Inputs
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max.
,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f=0
L
Test Conditions
V
CC
= Min., I
OH
= – 4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.0
–0.5
–1
–2
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+1
+2
130
100
15
L
7
1
L
100
2.0
–0.5
–1
–2
Max.
7C1020V-12
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+1
+2
120
90
15
7
1
100
2.0
–0.5
–1
–2
Max.
7C1020V-15
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+1
+2
110
80
15
7
1
100
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
µA
I
SB1
I
SB2
Shaded areas contain advanced information
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “instant on” case temperature.
2
PRELIMINARY
Electrical Characteristics
Over the Operating Range (Continued)
7C1020V-20
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
— TTL Inputs
Automatic CE
Power-Down Current
— CMOS Inputs
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max.
,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f=0
L
Test Conditions
V
CC
= Min., I
OH
= – 4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.0
–0.5
–1
–2
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+1
+2
100
70
15
L
7
1
L
100
2.0
–0.5
–1
–2
Max.
CY7C1020V
7C1020V-25
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+1
+2
100
70
15
7
1
100
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
µA
I
SB1
I
SB2
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 3.3V
Max.
8
8
Unit
pF
pF
Notes:
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
3.3V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
OUTPUT
Equivalent to: THÉVENIN
EQUIVALENT
R2
255Ω
R 481
Ω
R 481Ω
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
167Ω
30 pF
R2
255Ω
GND
<3ns
1021-3
1021-4
ALL INPUT PULSES
3.0V
90%
10%
90%
10%
<3ns
1.73V
3
PRELIMINARY
Switching Characteristics
[4]
Over the Operating Range
7C1020V-10
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[5, 6]
CE LOW to Low Z
[6]
CE HIGH to High Z
[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte enable to Data Valid
Byte enable to Low Z
Byte disable to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[5, 6]
Byte enable to end of write
7
10
8
7
0
0
7
5
0
3
5
8
0
5
12
9
8
0
0
8
6
0
3
6
0
12
5
0
6
3
5
0
12
6
0
5
3
6
3
10
5
0
6
10
10
3
12
6
12
12
Description
Min.
Max.
7C1020V-12
Min.
Max.
CY7C1020V
7C1020V-15
Min.
15
15
3
15
7
0
7
3
7
0
15
7
0
7
15
10
10
0
0
10
10
0
3
7
9
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE
[7]
Shaded areas contain advanced information
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
4
PRELIMINARY
Switching Characteristics
[4]
Over the Operating Range (continued)
7C1020V-20
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
CE LOW to Low Z
[6]
CE HIGH to High Z
[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte enable to Data Valid
Byte enable to Low Z
Byte disable to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low
WE LOW to High
Z
[6]
Z
[5, 6]
12
20
12
12
0
0
12
10
0
3
9
14
0
9
25
15
15
0
0
15
15
0
3
0
20
9
0
0
3
9
0
3
20
9
0
3
20
20
3
25
Description
Min.
Max.
CY7C1020V
7C1020V-25
Min.
Max.
Unit
ns
25
25
11
ns
ns
ns
ns
ns
ns
11
25
11
11
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
ns
ns
WRITE CYCLE
[7]
Byte enable to end of write
Switching Waveforms
Read Cycle No.1
[8, 9]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1021-5
Notes:
8. Device is continuously selected. OE, CE, BHE and/or BHE = V
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