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5962R9660301V9A

产品描述4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, UUC14
产品类别逻辑    逻辑   
文件大小74KB,共9页
制造商Renesas(瑞萨电子)
官网地址https://www.renesas.com/
下载文档 详细参数 选型对比 全文预览

5962R9660301V9A概述

4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, UUC14

5962R9660301V9A规格参数

参数名称属性值
零件包装代码DIE
包装说明DIE, DIE OR CHIP
针数14
Reach Compliance Codeunknown
系列4000/14000/40000
JESD-30 代码R-XUUC-N14
JESD-609代码e0
负载电容(CL)50 pF
逻辑集成电路类型INVERTER
最大I(ol)0.00064 A
功能数量6
输入次数1
端子数量14
最高工作温度125 °C
最低工作温度-55 °C
封装主体材料UNSPECIFIED
封装代码DIE
封装等效代码DIE OR CHIP
封装形状RECTANGULAR
封装形式UNCASED CHIP
电源5/15 V
Prop。Delay @ Nom-Sup378 ns
传播延迟(tpd)378 ns
认证状态Not Qualified
施密特触发器YES
筛选级别MIL-PRF-38535 Class V
最大供电电压 (Vsup)18 V
最小供电电压 (Vsup)3 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子面层TIN LEAD
端子形式NO LEAD
端子位置UPPER
总剂量100k Rad(Si) V
Base Number Matches1

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CD40106BMS
December 1992
CMOS Hex Schmitt Triggers
Pinout
CD40106BMS
TOP VIEW
A 1
G=A 2
B 3
H=B 4
14 VDD
13 F
12 L = F
11 E
10 K = E
9 D
8 J=D
Features
• High Voltage Type (20V Rating)
• Schmitt Trigger Action with No External Components
• Hysteresis Voltage (Typ.)
- 0.9V at VDD = 5V
- 2.3V at VDD = 10V
- 3.5V at VDD = 15V
• Noise Immunity Greater than 50%
• No Limit on Input Rise and Fall Times
• Low VDD to VSS Current During Slow Input Ramp
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
C 5
I=C 6
VSS 7
Functional Diagram
A
1
2
G=A
B
3
4
H=B
Applications
• Wave and Pulse Shapers
• High Noise Environment Systems
• Monostable Multivibrators
C
5
6
I=C
D
9
8
J=D
E
11
10
K=E
• Astable Multivibrators
Description
CD40106BMS consists of six Schmitt trigger circuits. Each
circuit functions as an inverter with Schmitt trigger action on
the input. The trigger switches at different points for positive
and negative going signals. The difference between the
positive going voltage (VP) and the negative going voltage
(VN) is defined as hysteresis voltage (VH) (see Figure 17).
The CD40106BMS is supplied in these 14 lead outline
packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4Q
H1B
H3W
*
F
13
12
L=F
Logic Diagram
A
1 (3, 5, 9, 11, 13)
*
*
G
2 (4, 6, 8, 10, 12)
VDD
ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
VSS
FIGURE 1. 1 OF 6 SCHMITT TRIGGERS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3354
7-1327

5962R9660301V9A相似产品对比

5962R9660301V9A 5962R9660301VXC 5962R9660302VXC CD40106BHSR CD40106BKNSR
描述 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, UUC14 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, CDFP14 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, CDFP14, CERAMIC, DFP-14 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, CDIP14, METAL SEALED, CERAMIC, DIP-14 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, CDFP14, METAL SEALED, CERAMIC, DFP-14
零件包装代码 DIE DFP DFP DIP DFP
包装说明 DIE, DIE OR CHIP DFP, FL14,.3 DFP, FL14,.3 METAL SEALED, CERAMIC, DIP-14 DFP,
针数 14 14 14 14 14
Reach Compliance Code unknown unknown unknown not_compliant compliant
系列 4000/14000/40000 4000/14000/40000 4000/14000/40000 4000/14000/40000 4000/14000/40000
JESD-30 代码 R-XUUC-N14 R-CDFP-F14 R-CDFP-F14 R-CDIP-T14 R-CDFP-F14
逻辑集成电路类型 INVERTER INVERTER INVERTER INVERTER INVERTER
功能数量 6 6 6 6 6
输入次数 1 1 1 1 1
端子数量 14 14 14 14 14
最高工作温度 125 °C 125 °C 125 °C 125 °C 125 °C
最低工作温度 -55 °C -55 °C -55 °C -55 °C -55 °C
封装主体材料 UNSPECIFIED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
封装代码 DIE DFP DFP DIP DFP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 UNCASED CHIP FLATPACK FLATPACK IN-LINE FLATPACK
传播延迟(tpd) 378 ns 378 ns 378 ns 378 ns 378 ns
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
标称供电电压 (Vsup) 5 V 5 V 5 V 5 V 5 V
表面贴装 YES YES YES NO YES
技术 CMOS CMOS CMOS CMOS CMOS
温度等级 MILITARY MILITARY MILITARY MILITARY MILITARY
端子形式 NO LEAD FLAT FLAT THROUGH-HOLE FLAT
端子位置 UPPER DUAL DUAL DUAL DUAL
JESD-609代码 e0 e4 e4 - -
负载电容(CL) 50 pF 50 pF 50 pF - -
最大I(ol) 0.00064 A 0.00064 A 0.00064 A - -
封装等效代码 DIE OR CHIP FL14,.3 FL14,.3 - -
电源 5/15 V 5/15 V 5/15 V - -
Prop。Delay @ Nom-Sup 378 ns 378 ns 378 ns - -
施密特触发器 YES YES YES - -
筛选级别 MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V - -
最大供电电压 (Vsup) 18 V 18 V 18 V - -
最小供电电压 (Vsup) 3 V 3 V 3 V - -
端子面层 TIN LEAD GOLD GOLD - -
总剂量 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V - -
Base Number Matches 1 1 1 1 -
座面最大高度 - 2.92 mm - 5.08 mm 2.92 mm
端子节距 - 1.27 mm 1.27 mm 2.54 mm 1.27 mm
宽度 - 6.285 mm - 7.62 mm 6.285 mm

 
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