Section II. HardCopy
APEX Device Family Data
Sheet
This section provides designers with the data sheet specifications for
HardCopy
®
APEX
TM
devices. These chapters contain feature definitions
of the internal architecture, configuration and JTAG boundary-scan
testing information, DC operating conditions, AC timing parameters, a
reference to power consumption, and ordering information for
HardCopy APEX devices.
This section contains the following:
■
■
■
■
Chapter 7, Introduction to HardCopy APEX Devices
Chapter 8, Description, Architecture, and Features
Chapter 9, Boundary-Scan Support
Chapter 10, Operating Conditions
Revision History
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the complete handbook.
Altera Corporation
Section II–1
Preliminary
Revision History
HardCopy Series Handbook, Volume 1
Section II–2
Preliminary
Altera Corporation
7. Introduction to
HardCopy APEX Devices
H51006-2.3
Introduction
HardCopy
®
APEX
TM
devices enable high-density APEX 20KE device
technology to be used in high-volume applications where significant cost
reduction is desired. HardCopy APEX devices are physically and
functionally compatible with APEX 20KC and APEX 20KE devices. They
combine the time-to-market advantage, performance, and flexibility of
APEX 20KE devices with the ability to move to high-volume, low-cost
devices for production. The migration process from an APEX 20KE
device to a HardCopy APEX device is fully automated, with designer
involvement limited to providing a few Quartus
®
II software-generated
output files.
HardCopy APEX devices are manufactured using an 0.18-μm CMOS
six-layer-metal process technology:
■
■
■
■
■
■
■
Features...
■
Preserves functionality of a configured APEX 20KC or APEX 20KE
device
Pin-compatible with APEX 20KC or APEX 20KE devices
Meets or exceeds timing of configured APEX 20KE and APEX 20KC
devices
Optional emulation of original programmable logic device (PLD)
programming sequence
High-performance, low-power device
MultiCore architecture integrating embedded memory and look-up
table (LUT) logic used for register-intensive functions
Embedded system blocks (ESBs) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port RAM,
and content-addressable memory (CAM)
Customization performed through metallization layers
Altera Corporation
September 2008
7–1
HardCopy Series Handbook, Volume 1
High-density architecture:
■
■
■
400,000 to 1.5 million typical gates (Table
7–1)
Up to 51,840 logic elements (LEs)
Up to 442,368 RAM bits that can be used without reducing available
logic
Table 7–1. HardCopy APEX Device Features
Feature
Maximum system gates
Typical gates
LEs
ESBs
Maximum RAM bits
Phase-locked loops (PLLs)
Maximum macrocells
Maximum user I/O pins
Note to
Table 7–1:
(1)
Note (1)
HC20K600
1,537,000
600,000
24,320
152
311,296
4
2,432
588
HC20K400
1,052,000
400,000
16,640
104
212,992
4
1,664
488
HC20K1000
1,772,000
1,000,000
38,400
160
327,680
4
2,560
708
HC20K1500
2,392,000
1,500,000
51,840
216
442,368
4
3,456
808
The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to
57,000 additional gates.
...and More
Features
Low-power operation:
■
■
■
1.8-V supply voltage (Table
7–2)
MultiVolt I/O support for 1.8-, 2.5-, and 3.3-V interfaces
ESBs offering power-saving mode
Flexible clock management circuitry with up to four phase-locked loops
(PLLs):
■
■
■
■
■
Built-in low-skew clock tree
Up to eight global clock signals
ClockLock feature reducing clock delay and skew
ClockBoost feature providing clock multiplication and division
ClockShift feature providing clock phase and delay shifting
Powerful I/O features:
■
Compliant with peripheral component interconnect Special Interest
Group (PCI SIG)
PCI Local Bus Specification, Revision 2.2
for 3.3-V
operation at 33 or 66 MHz and 32 or 64 bits
7–2
Altera Corporation
September 2008
...and More Features
■
■
■
■
■
■
■
■
Support for high-speed external memories, including double-data
rate (DDR), synchronous dynamic RAM (SDRAM), and
zero-bus-turnaround (ZBT) static RAM (SRAM)
16 input and 16 output LVDS channels
Fast
t
CO
and
t
SU
times for complex logic
MultiVolt I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces
Individual tri-state output enable control for each pin
Output slew-rate control to reduce switching noise
Support for advanced I/O standards, including LVDS, LVPECL,
PCI-X, AGP, CTT, SSTL-3 and SSTL-2, GTL+, and HSTL Class I
Supports hot-socketing operation
Table 7–2. HardCopy APEX Device Supply Voltages
Feature
Internal supply voltage (V
CCINT
)
MultiVolt I/O interface voltage levels (V
CCIO
)
Note to
Table 7–2:
(1)
HardCopy APEX devices can be 5.0-V tolerant by using an external resistor.
Voltage
1.8 V
1.8 V, 2.5 V, 3.3 V, 5.0 V
(1)
HardCopy APEX device implementation features:
■
■
■
■
Customized interconnect for each design
HardCopy APEX devices preserve APEX 20K device MegaLAB
structure, LEs, ESBs, I/O element (IOE), PLLs, and LVDS circuitry
Up to four metal layers customizable for customer designs
Completely automated proprietary design migration flow
●
Testability analysis and fix
●
Automatic test pattern generation (ATPG)
●
Automatic place and route
●
Static timing analysis
●
Static functional verification
●
Physical verification
Altera Corporation
September 2008
7–3
嵌入式系统
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