THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
APRIL 1995
MA17501
DS3564-3.4
MA17501
RADIATION HARD MIL-STD-1750A EXECUTION UNIT
The MA17501 Execution Unit is a component of the GEC
Plessey Semiconductors MAS281 chip set. Other chips in the
set include the MA17502 Control Unit and the MA17503
lnterrupt Unit. Also available is the peripheral MA31751
Memory Management Unit/Block Protection Unit. These chips
in conjunction implement the full MlL-STD-1750A lnstruction
Set.
The MA17501 - consisting of a full function 16-bit ALU, 24 x
16-bit dual-port RAM register file, 32-bit barrel shifter, 4 x 24-
bit parallel multiplier, synchronisation clock generation logic,
and microcode decode logic - provides all computational,
logical, and synchronisation functions for the chip set. Table 1
provides brief signal definitions.
The MA17501 is offered in several package styles
including; dual-in-line, flatpack and leadless chip carrier. Full
packaging information is given at the end of the document.
BLOCK DIAGRAM
FEATURES
s
MIL-STD-1750A Instruction Set Architecture
s
Full Performance over Military Temperature Range
(-55°C to +125°C)
s
Radiation Hard CMOS/SOS Technology
s
16-Bit Bidirectional Address/Data Bus
s
16-Bit Full Function Registered ALU
s
32-Bit Barrel Shifter
s
24 x 16-Bit Dual-Port RAM File
• 16 User Accessible General Purpose Registers
• 8 Microcode Accessible Registers
s
4 x 24-Bit Parallel Multiplier
• 48-Bit Accumulator
• 16-Bit x 16-Bit Multiply in 4 Machine Cycles
s
Instruction Pre-Fetch
s
MAS281 Integrated Built-in Self Test
s
TTL Compatible System Interface
1.0 SYSTEM CONSIDERATIONS
The MA17501 Execution Unit (EU) is a component of the
GEC Plessey Semiconductors MAS281 chip set. This chip set
implements the full MlL-STD-1750A instruction set
architecture. The other chips in the set are the MA17502
Control Unit (CU) and the MA17503 Interrupt Unit (IU). Also
available is the peripheral MA31751 Memory Management
Unit/Block Protection Unit (MMU(BPU)).
Figure 1 depicts the relationship between the chip set
components. The EU provides the arithmetic and logical
computation resources for the chip set. The EU also provides
program sequencing logic in support of branching and
subroutine functions. The lU provides interrupt and fault
handling resources, DMA interface control signals, and the
three MIL-STD-1750A timers. The EU and lU are each
controlled by microcode from the CU. The MMU(BPU) may be
configured to provide 1M-word memory management (MMU)
and/or 1K-word memory block write protection (BPU)
functions.
1
MA17501
Figure 1: MAS281 Chip Set with Optional MA17504 and Support RAMs
As shown in Figure 1, the MAS281 is the minimum
processor configuration consisting of an Execution Unit, a
Control Unit, and an Interrupt Unit. This configuration is
capable of accessing a 64K-word address space. Addition of a
MA31751 allows access to a 1M-word address space and/or
provides hardware support for 1K-word memory block write
protection.
The EU, as with all components of the MAS281 chip set, is
fabricated with GEC Plessey Semiconductors CMOS/SOS
process technology. lnput and output buffers associated with
signals external to the MAS281 are TTL compatible.
Detailed descriptions of the EU's companion chips are
provided in separate data sheets. Additional discussions on
chip set system considerations, interconnection details, and
DAlS mix benchmarking analysis are provided in separate
applications notes.
The Execution Unit consists of a full function 16-bit ALU,
32-bit barrel shifter, 4 x 24-bit parallel multiplier, 24 x 16bit
dual-port RAM register file, processor status word register,
three operand transfer registers, three instruction fetch
registers, various interconnect buses, synchronization clock
generation logic, and microcode decode logic. Details of these
components are depicted in Figure 2 and are discussed below:
2.0 ARCHITECTURE
2.1 ALU
The ALU is a full function 16-bit arithmetic/logic unit
capable of performing arithmetic and logic operations on either
one or two 16-bit operands in a single machine cycle. ln
addition to operand manipulation, the ALU is used to compute
memory addresses.
The ALU supports 16-bit fixed-point single-precision, 32-bit
fixed-point double-precision, 32-bit floating-point, and 48-bit
floating-point extended-precision data in two’s complement
representation. Double-precision and extended-precision
operands are passed through the ALU 16 bits at a time on
consecutive machine cycles. Machine flags provide an
indication of ALU results and are used to set condition status
(CS) bits C, P, Z, and N in the Status Word Register. Condition
status bits and the Status Word register are discussed below.
2
MA17501
Signal
AD00 - AD15
AS
CLKPC
CLK02
PAUSE
DS
HLDAK
HOLD
lN/OP
INTRE
lRDY
M/lO
M00 - M19
OSC
OVl
PlF
RD/W
RDY
RESET
SYNCLK
SYNC
SYSCLK1
TEST
T1
VDD
GND
I/O
I/O
O/Z
O
O
l
O/Z
O
l
O/Z
O
l
O/Z
l
l
O
l
O/Z
l
l
O
O
O
I
O
Definition
External 16-Bit Address/Data Bus
Address Strobe Indicates Address lnformation on A/D Bus
Precharge Clock
Phase 2 Clock
DMA Acknowledge (A/D Bus to be used for DMA)
Data Strobe lndicates Data lnformation on A/D Bus
Hold Acknowledge
Hold Request Suspends lnternal Processor Functions
lnstruction/Operand lndicates Type of Memory Access
lnterrupt Enable
lnterrupt Unit Ready Signal
Memory or lnput/Output lndicates Transaction on A/D Bus
20-Bit Microcode Bus
External Oscillator Clock
Overflow lndicator
Privileged Instruction Fault
Read/Write IndicatesData Direction on A/D Bus
Ready lnforms CPU of the Conclusion of External Bus Cycle
Reset Indicates Device Initialization
Interrupt Unit's Sync Clock
System Clock - CPU Sync Clock (External)
System Clock (Internal)
Test Enable
Branch or Jump Control
Power (External), 5 Volts
Ground
Table 1: Signal Definitions
2.2 BARREL SHIFTER
The Barrel Shifter is a 32-bit input, 16-bit output right shift
network. A 32-bit operand may be shifted right arithmetically,
logically, or cyclically up to 31 bit positions in a single machine
cycle. While not directly accessible or visible to user programs,
the Barrel Shifter is utilized by microcode to effect all shift,
rotate, and normalize instructions with minimum execution
time.
2.3 PARALLEL MULTIPLIER
The Parallel Multiplier performs a 4-bit multiplier by 24-bit
multiplicand multiplication plus accumulation in a single
machine cycle. Only four machine cycles are required to
complete a 16-bit by 16-bit multiplication. Contained within the
multiplier is a 48-bit product accumulation register with the
lower 24 bits serving as a source operand register.
On each multiply machine cycle, the lower four bits of the
accumulator are multiplied by 24 bits from the two ALU
operand source buses (R and S). The lower 24 bits of this 28-
bit product are then added to the upper 24 bits of the
accumulator and the whole accumulator is shifted right four
bits. This right shift makes room for the upper four bits of the
product. The four bits shifted out are used in the next multiply
iteration.
2.4 DUAL-PORT REGISTER FILE
The Register File is a dual port RAM structure containing
24, 16-bit registers. Sixteen of these registers are general
purpose and user accessible. These user accessible registers
- referred to as R0 through R15 - may be used as
accumulators, index registers, base registers temporary
operand registers, or stack pointers. The remaining eight
registers are only accessible by microcode.
Adjacent registers are concatenated to effectively form 32-
bit and 48-bit registers for storage of double precision and
extended-precision operands, respectively. Instructions
access these operands by specifying the register containing
the most significant part of the operand, and the register set
wraps around automatically under microcode control, e.g.,
R15 concatenates with R0 for 32-bit operands and R15
concatenates with R0 and R1 for 48-bit operands.
3
MA17501
Figure 2: MA17501 Execution Unit Architecture
2.5 STATUS WORD REGISTER
The Status Word Register (SW) holds the condition status
(CS) bits C, P, Z, and N generated by ALU operations. The SW
also stores the address state (AS) and processor state (PS)
fields. Figure 3 defines the Status Word Register storage
format. The CS bits are stored with each logical, shift, and
arithmetic operation performed by the ALU as required by MlL-
STD-1750A and remain valid until changed by subsequent
operations. The CS bits are interrogated during "jump on
condition" and "instruction counter relative" MlL-STD-1750A
branch instructions.
2.6 OPERAND TRANSFER REGISTERS
The Address (A), Data Output (DO), and Data lnput (Dl)
registers are referred to as Operand Transfer Registers. These
registers serve as storage buffers between internal EU buses
and the EU's externally accessible address/data (AD) Bus.
The DO register buffers data transferred from the EU to the AD
Bus. The A register buffers operand addresses and XlO
commands onto the AD Bus. The Dl register buffers data
transferred from the AD Bus to the EU .
4
FPGA/CPLD
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