CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Electrical Specifications
PARAMETER
SUPPLY
V
S
I
S
V
DD
= 5V, V
BOOST
= 11V, I
LOAD
= 200mA, V
ON
= 15V, V
OFF
= -5V, V
LOGIC
= 2.5V, limits over -40°C to
+105°C temperature range, unless otherwise specified.
CONDITION
MIN
TYP
MAX
UNIT
DESCRIPTION
Supply Voltage
Quiescent Current
Enabled, LX not switching
Disabled
3
1.7
750
5.5
2.5
900
V
mA
µA
CLOCK
f
OSC
BOOST
V
BOOST
V
FBB
Boost Output Range
Boost Feedback Voltage
T
A
= +25°C
5.5
1.192
1.188
V
F_FBB
V
REF
FBB Fault Trip Point
Reference Voltage
T
A
= +25°C
1.19
1.187
D
MAX
I
LXMAX
I
LEAK
r
DS(ON)
Eff
I(V
FBB
)
ΔV
BOOST
/ΔV
IN
Maximum Duty Cycle
Current Switch
Switch Leakage Current
Switch ON-Resistance
Boost Efficiency
Feedback Input Bias Current
Line Regulation
See curves
Pl mode, V
FBB
= 1.35V
C
INT
= 4.7nF, I
OUT
= 100mA, V
IN
= 3V to 5.5V
C
INT
pin strapped to V
DD
,
50mA < I
LOAD
< 250mA
C
INT
= 4.7nF, 50mA < I
O
< 250mA
85
V
LX
= 16V
320
92
50
0.05
3
0.1
4.7
4.8
500
85
2.0
10
1.205
1.205
0.9
1.215
1.215
1.235
1.238
20
1.218
1.222
V
V
V
V
V
V
%
A
µA
mΩ
%
nA
%/V
%
%
V
Oscillator Frequency
900
1000
1100
kHz
ΔV
BOOST
/ΔI
BOOST
Load Regulation - “P” Mode
ΔV
BOOST
/ΔI
BOOST
Load Regulation - “PI” Mode
V
CINT_T
V
ON
LDO
V
FBP
FBP Regulation Voltage
CINT Pl Mode Select Threshold
I
DRVP
= 0.2mA, T
A
= +25°C
I
DRVP
= 0.2mA
1.176
1.172
0.82
-250
1.2
1.2
0.87
1.224
1.228
0.92
250
V
V
V
nA
ms
V
F_FBP
I
FBP
GMP
FBP Fault Trip Point
FBP Input Bias Current
V
FBP
falling
V
FBP
= 1.35V
FBP Effective Transconductance V
DRVP
= 25V, I
DRVP
= 0.2mA to 2mA
50
2
FN6501.0
May 30, 2007
ISL78010
Electrical Specifications
PARAMETER
ΔV
ON
/ΔI(V
ON
)
I
DRVP
I
L_DRVP
V
OFF
LDO
V
FBN
FBN Regulation Voltage
I
DRVN
= 0.2mA, T
A
= +25°C
I
DRVN
= 0.2mA
V
F_FBN
I
FBN
GMN
ΔV
OFF
/
ΔI(V
OFF
)
I
DRVN
I
L_DRVN
V
LOGIC
LDO
V
FBL
FBL Regulation Voltage
I
DRVL
= 1mA, T
A
= +25°C
I
DRVL
= 1mA
V
F_FBL
I
FBL
G
ML
ΔV
LOGIC
/
ΔI(V
LOGIC
)
I
DRVL
I
L_DRL
SEQUENCING
t
ON
t
SS
t
DEL1
t
DEL2
I
DELB
Turn On Delay
Soft-start Time
Delay Between A
VDD
and V
OFF
Delay Between V
ON
and V
OFF
DELB Pull-down Current
C
DLY
= 0.22µF
C
DLY
= 0.22µF
C
DLY
= 0.22µF
C
DLY
= 0.22µF
V
DELB
> 0.6V
V
DELB
< 0.6V
FAULT DETECTION
t
FAULT
OT
I
PG
Fault Time Out
Over-temperature Threshold
PG Pull-down Current
VPG > 0.6V
VPG < 0.6V
LOGIC ENABLE
V
HI
V
LO
I
LOW
I
HIGH
Logic High Threshold
Logic Low Threshold
Logic Low Bias Current
Logic High Bias Current
at V
EN
= 5V
12
0.2
18
2.3
0.8
2
24
V
V
µA
µA
C
DLY
= 0.22µF
50
140
15
1.7
ms
°C
µA
mA
30
2
10
17
50
1.4
ms
ms
ms
ms
µA
mA
FBL Fault Trip Point
FBL Input Bias Current
FBL Effective Transconductance
V
LOGIC
Load Regulation
DRVL Sink Current Max
I
L_DRVL
V
FBL
falling
V
FBL
= 1.35V
V
DRVL
= 2.5V, I
DRVL
= 1mA to 8mA
I(V
LOGIC
) = 100mA to 500mA
V
FBL
= 1.1V, V
DRVL
= 2.5V
V
FBL
= 1.5V, V
DRVL
= 5.5V
8
1.176
1.174
0.82
-500
200
0.5
16
0.1
5
1.2
1.2
0.87
1.224
1.226
0.92
500
V
V
V
nA
mS
%
mA
µA
FNN Fault Trip Point
FBN Input Bias Current
V
FBN
falling
V
FBN
= 0.2V
0.173
0.171
0.38
-250
50
-0.5
2
4
0.1
5
0.203
0.203
0.43
0.233
0.235
0.48
250
V
V
V
nA
mS
%
mA
µA
V
DD
= 5V, V
BOOST
= 11V, I
LOAD
= 200mA, V
ON
= 15V, V
OFF
= -5V, V
LOGIC
= 2.5V, limits over -40°C to
+105°C temperature range, unless otherwise specified.
(Continued)
CONDITION
I(V
ON
) = 0mA to 20mA
V
FBP
= 1.1V, V
DRVP
= 25V
V
FBP
= 1.5V, V
DRVP
= 35V
2
MIN
TYP
-0.5
4
0.1
5
MAX
UNIT
%
mA
µA
DESCRIPTION
V
ON
Load Regulation
DRVP Sink Current Max
DRVP Leakage Current
FBN Effective Transconductance V
DRVN
= -6V, I
DRVN
= 0.2mA to 2mA
V
OFF
Load Regulation
DRVN Source Current Max
DRVN Leakage Current
I(V
OFF
) = 0mA to 20mA
V
FBN
= 0.3V, V
DRVN
= -6V
V
FBN
= 0V, V
DRVN
= -20V
3
FN6501.0
May 30, 2007
ISL78010
Pin Descriptions
PIN NAME
1, 2, 4, 6, 8, 10, 12,
16, 18, 23, 32
3
5
9
7
11
13
14, 27
15
17
19, 20, 21, 22
24
25
26
28
29
30
31
PIN NUMBER
NC
DELB
LX
FBP
DRVP
DRVL
FBL
SGND
DRVN
FBN
PGND
VREF
CINT
FBB
EN
VDD
PG
CDLY
Not connected
Open drain output for gate drive of optional V
BOOST
delay FET
Drain of the internal N-Channel boost FET
Positive LDO voltage feedback input pin; regulates to 1.2V nominal
Positive LDO base drive; open drain of an internal N-Channel FET
Logic LDO base drive; open drain of an internal N-Channel FET
Logic LDO voltage feedback input pin; regulates to 1.2V nominal
Low noise signal ground
Negative LDO base drive; open drain of an internal P-Channel FET
Negative LDO voltage feedback input pin; regulates to 0.2V nominal
Power ground, connected to source of internal N-Channel boost FET
Bandgap reference output voltage; bypass with a 0.1µF to SGND
V
BOOST
integrator output; connect capacitor to SGND for PI-mode or connect to V
DD
for P-mode
operation
Boost regulator voltage feedback input pin; regulates to 1.2V nominal
Enable pin; High = Enable; Low or floating = Disable
Positive supply
Push-pull gate drive of optional fault protection FET; when chip is disabled or when a fault has been
detected, this is high
A capacitor connected from this pin to SGND sets the delay time for start-up sequence and sets the fault
射频识别(Radio Frequency Identification，RFID)技术是一种利用无线射频通信实现的非接触式自动识别技术，与目前广泛采用的条形码技术相比，RFID具有容量大、识别距离远、穿透能力强、抗污性强等特点。RFID技术已经发展得比较成熟并获得了大规模商用，但超高频RFID技术相对滞后。本文分析了射频芯片nRF9E5的功能特性，并将其用于RFID系统中，设计了一套有源超高频(...[详细]
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