IS71VPCF32
X
S04
3.0 Volt-Only Flash & SRAM COMBO with Stacked Multi-Chip
Package (MCP) — 32 Mbit Simultaneous Operation Flash
Memory and 4 Mbit Static RAM
MCP FEATURES
•
Power supply voltage 2.7V to 3.3V
•
High performance:
Flash: 70ns maximum access time
SRAM: 70ns maximum access time
ISSI
•
Over 100,000 write/erase cycles
•
Low supply voltage (Vccf
≤
2.5V) inhibits writes
•
WP/ACC
input pin:
If V
IL
, allows protection of boot sectors
If V
IH
, allows removal of boot sector protection
If Vacc, program time is reduced by 40%
®
PRELIMINARY INFORMATION
AUGUST 2002
•
Package: 73-ball BGA
•
Operating Temperature: -40C to +85C
•
Boot sector: Top or Bottom
FLASH FEATURES
•
Power Dissipation:
Read Current at 1 Mhz: 7 mA maximum
Read Current at 5 Mhz: 18 mA maximum
Sleep Mode: 5
µA
maximum
SRAM FEATURES (4 Mb density)
•
Power Dissipation:
Operating: 40 mA maximum
Standby: 7 µA maximum
Chip Selects:
CE1s,
CE2s
Power down feature using
CE1s,
or CE2s
Data retention supply voltage: 1.5 to 3.3 volt
Byte data control:
LBs
(DQ0–DQ7),
UBs
(DQ8–DQ15) — in x16 mode
•
Simultaneous Read and Write Operations:
Zero latency between read and write operations; Data
can be programmed or erased in one bank while data
is simultaneously being read from the other bank
•
•
•
•
•
Low-Power Mode:
A period of no activity causes flash to enter a
low-power state
•
Erase Suspend/Resume:
Suspends of erase activity to allow a read in the
same bank
GENERAL DESCRIPTION
The flash and SRAM MCP is available in 32 Mbit Flash/4
Mbit SRAM having a data bus of either x8 or x16. The 32
Mbit flash is composed of 2,097,152 words of 16 bits or
4,194,304 bytes of 8 bits. The 4Mb SRAM has 262,144
words of 16 bits or 524,288 bytes of 8 bits. Data lines DQ0-
DQ7 handle the x8 format, while lines DQ0-DQ15 handle
the x16 format.
The package uses a 3.0V power supply for all operations.
No other source is required for program and erase opera-
tions. The flash can be programmed in system using this
3.0V supply, or can be programmed in a standard EPROM
programmer.
The 32 Mbit flash/4 Mbit SRAM is offered in a 73-pin BGA
package. The flash is compatible with the JEDEC Flash
command set standard . The flash access time is 70ns or
85ns and the SRAM access time is 70ns or 85ns.
The Flash architecture is composed of two banks which
allows simultaneous operation on each. Optimized per-
formance can be achieved by first initializing a program or
erase function in one bank, then immediately starting a
read from the other bank. Both operations would then be
operating simultaneously, with zero latency.
•
Sector Erase Architecture:
8 words of 4k size and 63 words of 32K size (32 Mbit)
Any combination of sectors, or the entire flash can
be simultaneously erased
•
Erase Algorithms:
Automatically preprograms/erases the flash memory
entirely, or by sector
•
Program Algorithms:
Automatically writes and verifies data at specified
address
•
Hidden ROM Region:
64KB with a Factory-serialized secure electronic
serial number (ESN), which is accessible through a
command sequence
•
Data Polling and Toggle Bit:
Allow for detection of program or erase cycle
completion
•
Ready-Busy output (RY/BY)
Detection of program or erase cycle completion
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
08/01/02
1
IS71VPCF32
X
S04
ISSI
WE
SA
(6)
LB
LBs
UBs
UB
DQ
0-
DQ
7
DQ
8
-DQ
15
RESET WP
/ACC
(5)
®
DEVICE BUS OPERATIONS
User Bus Operations (Flash=Word mode: I/Of = Vccf, SRAM= Word Mode: I/Os = Vccs)
OPERATION
(1,3)
Full Standby
Output Disable
CEf CE1s
CE CE
CE2s
OE
Read from Flash
(2)
Write to Flash
Read from SRAM
Write to SRAM
Temporary Sector
Group Unprotection
(4)
Flash Hardware
X
Reset
X
Boot Block Sector
X
Write Protection
Notes:
1.
2.
3.
4.
5.
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
X
H
X
L
L
H
X
H
X
H
X
L
L
L
L
L
L
X
H
X
X
X
L
H
H
X
L
X
L
X
L
H
H
H
H
H
H
X
X
L
X
X
X
H
X
H
H
L
L
H
H
L
L
L
X
X
X
X
X
X
X
X
X
H
X
H
H
H
H
L
L
H
H
H
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
L
H
L
L
H
L
X
X
X
X
X
X
X
H
X
X
X
X
X
X
L
L
H
L
L
H
X
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
D
OUT
D
OUT
D
IN
D
IN
D
OUT
High-Z
D
OUT
D
IN
High-Z
D
IN
X
High-Z
High-Z
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
D
OUT
D
OUT
D
IN
D
IN
D
OUT
D
OUT
High-Z
D
IN
D
IN
High-Z
X
High-Z
High-Z
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
V
ID
(8)
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
Any operations not indicated this column are inhibited.
WE
can be VIL if
OE
is VIL,
OE
at VIH initiates the write operations.
Do not apply
CEf
= VIL,
CE1s
= VIL and CE2s = VIH all at once.
It is also used for the extended sector group protections.
WP/ACC
= VIL: protection of boot sectors.
WP/ACC
= VIH: removal of boot sectors protection.
WP/ACC
= VACC (9V): Program time will reduce by 40%.
6. SA: Don’t care or open.
7. L = VIL, H = VIH, X = VIL or VIH.
8. See DC CHARACTERISTICS.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
08/01/02
5
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