CDP6805E2, CDP6805E2C,
CDP6805E3, CDP6805E3C
March 1998
CMOS 8-Bit Microprocessor
Description
The CDP6805E2 and CDP6805E3 Microprocessors Unit
(MPUs) belong to the CDP6805 Family of CMOS
Microcomputers. These 8-bit fully static and expandable
microprocessors contain a CPU, on-chip RAM, I/O and
Timer. They are low power, low cost processors designed for
mid-range applications in the consumer, automotive,
industrial and communications markets where very low
power consumption constitutes an important factor. The
major features of the CDP6805E2 and CDP6805E3 MPUs
are listed under “Hardware Features” and “Software
Features”.
Hardware Features
• Full Speed Operating Power @ 5V . . . . . . . 35mW(Typ)
• Wait Mode Power . . . . . . . . . . . . . . . . . . . . . . 5mW(Typ)
• Stop Mode Power . . . . . . . . . . . . . . . . . . . . . . 25µW(Typ)
• 112 Bytes of On-Chip RAM
• 16 Bidirectional I/O Lines on CDP6805E2
• 13 Bidirectional I/O Lines on CDP6805E3
• Internal 8-Bit Timer with Software Programmable 7-Bit
Prescaler
• External Timer Input
• Full External and Timer Interrupts
• Multiplexed Address/Data Bus
• Master Reset and Power-On Reset
• CDP6805E2 is Capable of Addressing up to 8K Bytes
of External Memory
• CDP6805E3 is Capable of Addressing up to 64K Bytes
of External Memory
• Single 3V to 6V Supply
• On-Chip Oscillator
• 40 Pin Dual-in-Line Package (E Suffix)
Ordering Information
PART NUMBER
CDP6805E2E
CDP6805E3E
CDP6805E2CE
CDP6805E3CE
CDP6805E2
CDP6805E3
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
PACKAGE
40 Ld PDIP
40 Ld PDIP
40 Ld PDIP
40 Ld PDIP
44 Ld PLCC
44 Ld PLCC
44 Ld PLCC
44 Ld PLCC
PKG.
NO.
E40.6
E40.6
E40.6
E40.6
N44.65
N44.65
N44.65
N44.65
• 44 Lead Plastic Chip Carrier Package (Q Suffix)
• -40
o
C to +85
o
C Operation with CDP6805E2C and
CDP6805E3C
CDP6805E2C
CDP6805E3C
Software Features
• Efficient Use of Program Space
• Versatile Interrupt Handling
• True Bit Manipulation
• Addressing Modes with Indexed Addressing for
Tables
• Efficient Instruction Set
• Memory Mapped I/O
• Two Power Saving Standby Modes
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
2746.3
1
CDP6805E2, CDP6805E2C, CDP6805E3, CDP6805E3C
Pinouts
CDP6805E2 (PDIP)
TOP VIEW
RESET
IRQ
LI
DS
R/W
AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
A12
A11
A10
A9
A8
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 V
DD
39 OSC1
38 OSC2
37 TIMER
36 PB0
35 PB1
34 PB2
33 PB3
32 PB4
31 PB5
30 PB6
29 PB7
28 B0
27 B1
26 B2
25 B3
24 B4
23 B5
22 B6
21 B7
CDP6805E3 (PDIP)
TOP VIEW
RESET
IRQ
LI
DS
R/W
AS
A15
A14
A13
PA4
PA3
PA2
PA1
PA0
A12
A11
A10
A9
A8
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 V
DD
39 OSC1
38 OSC2
37 TIMER
36 PB0
35 PB1
34 PB2
33 PB3
32 PB4
31 PB5
30 PB6
29 PB7
28 B0
27 B1
26 B2
25 B3
24 B4
23 B5
22 B6
21 B7
2
CDP6805E2, CDP6805E2C, CDP6805E3, CDP6805E3C
Pinouts
(Continued)
CDP6805E2 (PLCC)
TOP VIEW
RESET
TIMER
OSC1
OSC2
V
DD
PB0
R/W
IRQ
2
NC
DS
4
LI
3
6
AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
NC
NC
7
8
9
10
11
12
13
14
15
16
17
5
1 44 43 42 41 40
39
PB1
PB2
PB3
PB4
PB5
PB6
PB7
B0
B1
B2
B3
PIN 1 IDENT
38
37
36
35
34
33
32
31
30
29
18 19 26 25 24 23 22 21 20 27 28
A12
A11
A10
V
SS
NC
PB0
A9
A8
B7
B6
B5
OSC2
B4
TIMER
CDP6805E3 (PLCC)
TOP VIEW
RESET
OSC1
V
DD
R/W
IRQ
2
NC
DS
4
LI
3
6
AS
A15
A14
A13
PA4
PA3
PA2
PA1
PA0
NC
NC
7
8
9
10
11
12
13
14
15
16
17
5
1 44 43 42 41 40
39
PB1
PB2
PB3
PB4
PB5
PB6
PB7
B0
B1
B2
B3
PIN 1 IDENT
38
37
36
35
34
33
32
31
30
29
18 19 26 25 24 23 22 21 20 27 28
A12
A11
A10
V
SS
NC
A9
A8
B7
B6
B5
B4
3
CDP6805E2, CDP6805E2C, CDP6805E3, CDP6805E3C
Block Diagrams
TIMER
37
PRESCALER
7
TIMER/
8 COUNTER
OSC1
39
OSC2
38
RESET LI
1
3
IRQ
2
TIMER CONTROL
PA0
PA1
PA2
PORT A
PA3
I/O
LINES PA4
PA5
PA6
PA7
14
13
12
11
10
9
8
7
6
PORT
A
REG
DATA
DIR
REG
OSCILLATOR
28
B0
B1
B2
MULTIPLEXED
ADDRESS/
B4 DATA BUS
B3
B5
B6
B7
A8
A9
A10
A11
A12
AS
DS
ADDRESS
STROBE
DATA STROBE
(φ2)
ADDRESS
BUS
ACCUMULATOR
8
A
8
INDEX
REGISTER
X
CPU
CONTROL
MUX
BUS
DRIVE
CPU
27
26
25
24
23
22
21
19
18
CONDITION
CODE
REGISTER CC
5
STACK
POINTER SP
PROGRAM
COUNTER
HIGH PCH
5
PB0
PB1
36
35
34
PORT
B
REG
DATA
DIR
REG
PROGRAM
COUNTER
LOW
8
PCL
ALU
ADDRESS
DRIVE
17
16
15
6
PB2
PORT B PB3 33
I/O
32
LINES PB4
31
PB5
30
PB6
29
PB7
112 x 8
RAM
BUS
CONTROL
4
5
R/W READ/WRITE
FIGURE 1A. CDP6805E2 BLOCK DIAGRAM
TIMER
37
PRESCALER
7
TIMER/
8 COUNTER
OSC1
39
OSC2
38
RESET LI
1
3
IRQ
2
TIMER CONTROL
PA0
PORT A PA1
I/O
PA2
LINES
PA3
PA4
14
13
12
11
10
PORT
A
REG
DATA
DIR
REG
OSCILLATOR
28
B0
B1
B2
MULTIPLEXED
ADDRESS/
B4 DATA BUS
B3
B5
B6
B7
A8
A9
A10
A11 ADDRESS
BUS
A12
A13
A14
A15
AS
DS
ADDRESS
STROBE
DATA STROBE
(φ2)
ACCUMULATOR
8
A
8
INDEX
REGISTER
X
CPU
CONTROL
MUX
BUS
DRIVE
CPU
27
26
25
24
23
22
21
19
18
CONDITION
CODE
5 REGISTER CC
6
STACK
POINTER SP
PROGRAM
COUNTER
HIGH PCH
5
PB0
PB1
PB2
36
35
34
PORT
B
REG
DATA
DIR
REG
PROGRAM
COUNTER
LOW
8
PCL
ALU
ADDRESS
DRIVE
17
16
15
9
8
7
6
PORT B PB3 33
I/O
32
LINES PB4
31
PB5
30
PB6
29
PB7
112 x 8
RAM
BUS
CONTROL
4
5
R/W READ/WRITE
FIGURE 1B. CDP6805E3 BLOCK DIAGRAM
4
CDP6805E2, CDP6805E2C, CDP6805E3, CDP6805E3C
Absolute Maximum Ratings
DC Supply Voltage Range, (V
DD
) . . . . . . . . . . . . . . . . -0.3V to +8V
Voltage Referenced to V
SS
Terminal)
All Voltage Input Voltages Except OSC1 (V
IN)
. Vss-0.5V to V
DD
+0.5V
DC Input Current, Any One Input.
. . . . . . . . . . . . . . . . . . . . . . . .±10mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
Device Dissipation Per Output Transistor . . . . . . . . . . . . . . . 100mW
Maximum Storage Temperature Range (T
STG
) . . . .-55
o
C to 150
o
C
Maximum Lead Temperature (During Soldering) . . . . . . . . . . 265
o
C
At Distance 1/16
±1/32
in. (1.59
±
0.79mm)
From Case for 10s Max
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
CDP6805E2,CDP6805E2E,
CDP6805E3, CDP6805E3E . . . . . . . . . . . . . . . . . . . .0
o
C to 70
o
C
CDP6805E2C, CDP6805E2CE,
CDP6805E3C, CDP6805E3CE . . . . . . . . . . . . . . . -40
o
C to 85
o
C
T
A
= Full Package Temperature Range (All Package Types)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications 3.0V
(V
DD
= 3VDC, V
SS
= 0, T
A
= T
L
to T
H
), Unless Otherwise Specified
SYMBOL
V
OL
V
OH
MIN
-
V
DD
- 0.1
MAX
0.1
-
UNIT
V
V
PARAMETER
Output Voltage I
LOAD
≤
10µA
Total Supply Current (C
L
= 50pF - no DC loads) t
CYC
= 5µs
Run (V
IL
= 0.2V, V
IH
= V
DD
-0.2V)
Wait (Note 2)
Stop (Note 2)
Output High Voltage
(I
LOAD
= 0.25mA) A8-A15, B0-B7
(I
LOAD
= 0.1mA) PA0-PA7, PB0-PB7
(I
LOAD
= 0.25mA) DS, AS, R/W
Output Low Voltage
(I
LOAD
= 0.25mA) A8-A15, B0-B7
(I
LOAD
= 0.25mA) PA0-PA7, PB0-PB7
(I
LOAD
= 0.25mA) DS, AS, R/W
Input High Voltage
PA0-PA7, PB0-PB7, B0-B7
Timer, IRQ, RESET
OSC1
Input Low Voltage (All inputs)
Frequency of Operation
Crystal
External Clock
Input Current
RESET, IRQ, Timer, OSC1
I
IN
-
±1
µA
f
OSC
f
OSC
0.032
DC
1.0
1.0
MHz
MHz
V
IH
V
IH
V
IH
V
IL
2.1
2.5
2.1
-
-
-
-
0.5
V
V
V
V
V
OL
V
OL
V
OL
-
-
-
0.3
0.3
0.3
V
V
V
V
OH
V
OH
V
OH
2.7
2.7
2.7
-
-
-
V
V
V
I
DD
I
DD
I
DD
-
-
-
1.3
200
100
mA
µA
µA
5
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