24-bit System timer (Sys Tick): System timer for OS task
management
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
On-chip Memories
[Flash memory]
These series are based on two independent on-chip Flash
memories.
MainFlash
to 512 Kbyte
Built-in Flash Accelerator System with 16 Kbyte trace
buffer memory
The read access to Flash memory can be achieved without
wait cycle up to operation frequency of 72 MHz. Even at
the operation frequency more than 72 MHz, an equivalent
access to Flash memory can be obtained by Flash
Accelerator System.
Security function for code protection
Up
Operation mode is selectable from the followings for each
WorkFlash
32
Kbyte
cycle
4 wait-cycle: the operation frequency more than 72 MHz
2 wait-cycle: the operation frequency more than 40 MHz,
and to 72 MHz
0 wait-cycle: the operation frequency to 40 MHz
Security function is shared with code protection
Read
UART
double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control: Automatically control the
transmission by CTS/RTS (only ch.4)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
Full-duplex
[SRAM]
This Series contain a total of up to 64 Kbyte on-chip SRAM.
This is composed of two independent SRAM (SRAM0,
SRAM1). SRAM0 is connected to I-code bus and D-code bus
of Cortex-M3 core. SRAM1 is connected to System bus.
SRAM0:
CSIO
Full-duplex
Built-in
Up to 32 Kbyte
SRAM1: Up to 32 Kbyte
double buffer
dedicated baud rate generator
Overrun error detect function available
Cypress Semiconductor Corporation
Document Number: 002-05615 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February
9,
2018
MB9B410R Series
LIN
protocol Rev.2.1 supported
double buffer
Master/Slave mode supported
LIN break field generate (can be changed 13 to 16-bit
length)
LIN break delimiter generate (can be changed 1 to 4-bit
length)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
Full-duplex
LIN
General Purpose I/O Port
This series can use its pins as general purpose I/O ports
when they are not used for external bus or peripherals.
Moreover, the port relocate function is built in. It can set
which I/O port the peripheral function can be allocated.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up 103 fast general purpose I/O Ports @ 120 pin Package
Some pin is 5 V tolerant I/O.
See "4 List of Pin Functions" to confirm the corresponding
pins.
I
2
C
Standard-mode
kbps) supported
(Max 100 kbps) / Fast-mode (Max 400
DMA Controller (Eight channels)
DMA Controller has an independent bus for CPU, so CPU
and DMA Controller can process simultaneously.
Multi-function Timer (Max three units)
The Multi-function timer is composed of the following blocks.
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32-bit (4 Gbyte)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max 16 channels)
12-bit A/D Converter
Successive Approximation
Built-in
16-bit free-run timer × 3 ch./unit
Input capture × 4 ch./unit
Output compare × 6 ch./unit
A/D activating compare × 3 ch./unit
Waveform generator × 3 ch./unit
16-bit PPG timer × 3 ch./unit
The following function can be used to achieve the motor
control.
Register type
3 unit
Conversion time: 1.0 μs @ 5 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion: 4 steps)
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
Base Timer (Max eight channels)
Operation mode is selectable from the followings for each
channel.
Interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Document Number: 002-05615 Rev. *D
Page 2 of 112
MB9B410R Series
Quadrature Position/Revolution Counter (QPRC)
(Max three channels)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it
is possible to use up/down counter.
Clock and Reset
Clocks
Five clock sources (2 external oscillators, 2 internal CR
oscillator, and Main PLL) that are dynamically selectable.
Clock:
Sub Clock:
High-speed internal CR Clock:
Low-speed internal CR Clock:
Main
The detection edge of the three external event input pins AIN,
BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit
down counters.
Operation mode is selectable from the followings for each
channel.
4 MHz to 48 MHz
32.768 kHz
4 MHz
100 kHz
Resets
requests from INITX pin
Power on reset
Software reset
Watchdog timers reset
Low-voltage detector reset
Clock supervisor reset
Reset
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
Free-running
Periodic (=Reload)
One-shot
Watch Counter
The Watch counter is used for wake up from power
consumption mode.
External OSC clock failure (clock stop) is detected, reset is
asserted.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
External Interrupt Controller Unit
Up to 16 external interrupt input pin
Include one non-maskable interrupt (NMI)
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low-speed internal
CR oscillator. Therefore, "Hardware" watchdog is active in
any power consumption mode except Stop mode.
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Three power consumption modes supported.
Sleep
Timer
Stop
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM) provide comprehensive
debug and trace facilities.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or
storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
Power Supply
Wide range voltage:
VCC = 2.7 V to 5.5 V
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Document Number: 002-05615 Rev. *D
Page 3 of 112
MB9B410R Series
Table of Contents
Features .............................................................................................................................................................................. 1
List of Pin Functions ................................................................................................................................................. 13
5.
I/O Circuit Type .......................................................................................................................................................... 40
Precautions for Product Design ................................................................................................................................ 45
6.2
Precautions for Package Mounting ........................................................................................................................... 46
6.3
Precautions for Use Environment ............................................................................................................................. 48
Pin Status in Each CPU State ................................................................................................................................... 56
Absolute Maximum Ratings ...................................................................................................................................... 60
DC Characteristics .................................................................................................................................................... 63
12.3.1
Current Rating ....................................................................................................................................................... 63
AC Characteristics .................................................................................................................................................... 67
12.4.1
Main Clock Input Characteristics ........................................................................................................................... 67
12.4.2
Sub Clock Input Characteristics ............................................................................................................................. 68
External Bus Timing ............................................................................................................................................... 71
12.4.9
Base Timer Input Timing ........................................................................................................................................ 80
C Timing .............................................................................................................................................................. 92
Write / Erase time .................................................................................................................................................. 99
12.7.2
Erase/write cycles and data hold time.................................................................................................................... 99
Write / Erase time .................................................................................................................................................. 99
12.8.2
Erase/write cycles and data hold time.................................................................................................................... 99
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