HIGH-SPEED
32K x 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
IDT7007S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 25/35/55ns (max.)
— Commercial: 20/25/35/55ns (max.)
• Low-power operation
— IDT7007S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7007L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• IDT7007 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
•
•
•
•
•
•
•
•
•
more than one device
M/
S
= H for
BUSY
output flag on Master,
M/
S
= L for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Devices are capable of withstanding greater than 2001V
electrostatic discharge
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PGA, 68-pin PLCC, and a 80-pin
TQFP
Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
OE
L
R/
OE
R
CE
L
W
L
CE
R
R/
W
R
I/O
0L
- I/O
7L
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
BUSY
L(1,2)
A
14L
A
0L
Address
Decoder
15
BUSY
R
MEMORY
ARRAY
Address
Decoder
A
14R
A
0R
(1,2)
15
OE
L
R/
CE
L
W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
R/
OE
R
W
R
SEM
R
(2)
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
and
INT
outputs are non-tri-stated push-pull.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
M/
S
INT
R
2940 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2940/4
6.08
1
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION:
The IDT7007 is a high-speed 32K x 8 Dual-Port Static
RAM. The IDT7007 is designed to be used as a stand-alone
256K-bit Dual-Port RAM or as a combination MASTER/
SLAVE Dual-Port RAM for 16-bit-or-more word systems.
Using the IDT MASTER/SLAVE Dual-Port RAM approach in
16-bit or wider memory system applications results in full-
speed, error-free operation without the need for additional
discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by
CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 750mW of power.
The IDT7007 is packaged in a 68-pin pin PGA, a 68-pin
PLCC, and a 80-pin TQFP (thin plastic quad flatpack). Military
grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level
of performance and reliability.
PIN CONFIGURATIONS
(1,2)
I/O
1L
I/O
0L
N/C
SEM
L
4
L
INDEX
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
R/
9
8
7
6
5
3
A
14L
A
13L
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
OE
L
W
CE
L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
IDT7007
J68-1
PLCC
TOP VIEW(3)
54
53
52
51
50
49
48
47
46
45
BUSY
L
GND
M/
S
INT
R
BUSY
R
A
0R
A
1R
A
2R
A
3R
A
4R
2940 drw 02
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
OE
R
SEM
R
W
R
R/
CE
R
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to power supply.
3. This text does not indicate orientation of the actual part marking.
6.08
2
I/O
7R
N/C
A
14R
A
13R
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D.)
(1,2)
R/
L
I/O
1L
I/O
0L
N/C
SEM
L
INDEX
N/C
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
N/C
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
N/C
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
IDT7007
PN80-1
TQFP
TOP VIEW
(3)
N/C
A
14L
A
13L
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
N/C
N/C
OE
L
W
CE
L
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/
S
INT
R
BUSY
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
2940 drw 03
R/
R
I/O
7R
N/C
OE
R
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to power supply.
3. This text does not indicate orientation of the actual part marking.
SEM
R
N/C
A
14R
A
13R
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
N/C
N/C
6.08
CE
R
W
3
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D.)
(1,2)
51
11
53
A
7L
55
A
9L
A
5L
52
A
6L
54
A
8L
50
A
4L
49
A
3L
48
A
2L
47
A
1L
46
44
42
A
0L
BUSY
L
M/
S
45
40
38
A
1R
INT
R
36
A
3R
35
A
4R
32
A
7R
30
A
9R
34
A
5R
33
A
6R
31
A
8R
10
43
41
39
37
INT
L
GND
BUSY
R
A
0R
A
2R
09
08
56
57
A
11L
A
10L
58
59
V
CC
A
12L
61
60
A
13L
62
07
06
IDT7007
G68-1
68-PIN PGA
TOP VIEW
(3)
29
28
A
11R
A
10R
26
GND
27
A
12R
A
14L
63
05
SEM
L
65
CE
L
25
24
A
14R
A
13R
64
04
OE
L
R/
L
W
SEM
R
20
22
23
CE
R
03
67
66
I/O
0L
N/C
1
3
68
I/O
1L
I/O
2L
I/O
4L
2
4
I/O
3L
I/O
5L
B
C
5
7
9
11
13
15
GND I/O
7L
GND I/O
1R
V
CC
I/O
4R
6
I/O
6L
D
8
10
12
14
16
V
CC
I/O
0R
I/O
2R
I/O
3R
I/O
5R
E
F
G
H
J
OE
R
21
R/
R
W
02
18
19
I/O
7R
N/C
17
I/O
6R
K
01
A
INDEX
L
2940 drw 04
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part marking.
PIN NAMES
Left Port
Right Port
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2940 tbl 01
CE
L
R/
W
L
OE
L
A
0L
– A
14L
I/O
0L
– I/O
7L
CE
R
R/
W
R
OE
R
A
0R
– A
14R
I/O
0R
– I/O
7R
SEM
L
INT
L
BUSY
L
M/
S
V
CC
SEM
R
INT
R
BUSY
R
GND
6.08
4
IDT7007S/L
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE: NON-CONTENTION READ/WRITE CONTROL
Inputs
(1)
Outputs
CE
H
L
L
X
R/
W
X
L
H
X
OE
X
X
L
H
SEM
H
H
H
X
I/O
0-7
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected: Power-Down
Write to Memory
Read Memory
Outputs Disabled
Mode
NOTE:
1. A
0L
— A
14L
≠
A
0R
— A
14R.
2940 tbl 02
TRUTH TABLE: SEMAPHORE READ/WRITE CONTROL
(1)
Inputs
Outputs
CE
H
H
L
R/
W
H
X
OE
L
X
X
SEM
L
L
L
I/O
0-7
DATA
OUT
DATA
IN
—
Write I/O
0
into Semaphore Flag
Not Allowed
Mode
Read Semaphore Flag Data Out (I/O
0
-I/O
7
)
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from all I/O's (I/O
0
-I/O
7
). These eight semaphores are addressed by A
0
- A
2
.
2940 tbl 03
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
Rating
Commercial
Military
–0.5 to +7.0
Unit
V
Terminal Voltage –0.5 to +7.0
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
0 to +70
–55 to +125
–55 to +125
50
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Ambient
Temperature
–55°C to +125°C
0°C to +70°C
GND
0V
0V
V
CC
5.0V
±
10%
5.0V
±
10%
2940 tbl 05
T
A
T
BIAS
T
STG
I
OUT
–55 to +125
–65 to +135
–65 to +150
50
°C
°C
°C
mA
Commercial
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5.0
0
—
—
Max. Unit
5.5
0
6.0
(2)
0.8
V
V
V
V
2940 tbl 06
NOTES:
2940 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of V
TERM
> Vcc
+ 0.5V.
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.5V.
CAPACITANCE
(1)
(T
A
= +25°C, f = 1.0MHz)TQFP ONLY
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output
Capacitance
Conditions
(1)
Max.
V
IN
= 3dV
V
OUT
= 3dV
9
10
Unit
pF
pF
NOTES:
2940 tbl 07
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
6.08
5
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