HB526C264EN-10IN,
HB526C464EN-10IN
1,048,576-word
×
64-bit
×
2-bank Synchronous Dynamic RAM
Module
1,048,576-word
×
64-bit
×
4-bank Synchronous Dynamic RAM
Module
ADE-203-737B (Z)
Rev. 2.0
Mar. 14, 1997
Description
The HB526C264EN, HB526C464EN belong to 8-byte DIMM (Dual In-line Memory Module) family,
and have been developed as an optimized main memory solution for 8-byte processor applications. The
HB526C264EN is a 1M
×
64
×
2-bank Synchronous Dynamic RAM Module, mounted 8 pieces of 16-
Mbit SDRAM (HM5216805TT) sealed in TSOP package and 1 piece of serial EEPROM (24C02) for
Presence Detect (PD). The HB526C464EN is a 1M
×
64
×
4-bank Synchronous Dynamic RAM Module,
mounted 16 pieces of 16-Mbit SDRAM (HM5216805TT) sealed in TSOP package and 1 piece of serial
EEPROM (24C02) for Presence Detect (PD). An outline of the HB526C264EN, HB526C464EN are
168-pin socket type package (dual lead out). Therefore, the HB526C264EN, HB526C464EN make high
density mounting possible without surface mount technology. The HB526C264EN, HB526C464EN
provide common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the
module board.
Features
•
168-pin socket type package (dual lead out)
Outline: 133.37 mm (Length)
×
31.75 mm (Height)
×
2.92/4.00 mm (Thickness)
Lead pitch: 1.27 mm
•
3.3V power supply
•
Clock frequency: 66 MHz
•
JEDEC standard outline unbuffered 8-byte DIMM
•
LVTTL interface
•
Data bus width:
×
64 Non parity
•
2 Banks can operates simultaneously and independently
•
Burst read/write operation and burst read/single write operation capability
•
Programmable burst length: 1/2/4/8/full page
•
Programmable burst sequence
Sequential/interleave
HB526C264EN-10IN, HB526C464EN-10IN
•
Full page burst length capability
Sequential burst
Burst stop capability
•
Programmable
CE
latency: 2/3
•
4096 refresh cycles: 64 ms
•
2 variations of refresh
Auto refresh
Self refresh
Ordering Information
Type No.
HB526C264EN-10IN
HB526C464EN-10IN
Frequency
66 MHz
66 MHz
Package
168-pin dual lead out socket type
Contact pad
Gold
Pin Arrangement
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
Pin No.
1
2
3
4
5
6
7
8
Pin name
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
Pin No.
43
44
45
46
47
48
49
50
Pin name
V
SS
NC
S2
DQMB2
DQMB3
NC
V
DD
NC
Pin No.
85
86
87
88
89
90
91
92
Pin name
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
Pin No.
127
128
129
130
131
132
133
134
Pin name
V
SS
CKE0
NC (S3)*
3
DQMB6
DQMB7
NC
V
DD
NC
2
HB526C264EN-10IN, HB526C464EN-10IN
Pin Description
Pin name
A0 to A11
Function
Address input
Row address
Column address
DQ0 to DQ63
S0
to
S3
RE
CE
W
DQMB0 to DQMB7
CK0 to CK3 (CLK0 to CLK3)
CKE0, CKE1
SDA
SCL
SA0 to SA2
V
DD
V
SS
NC
Data input/output
Chip select input
Row enable (RAS) input
Column enable (CAS) input
Write enable input
Byte data mask
Clock input
Clock enable input
Data input/output for serial PD
Clock input for serial PD
Serial address input
Primary positive power supply
Ground
No connection
A0 to A10
A0 to A8
A11
Bank select address
4
HB526C264EN-10IN, HB526C464EN-10IN
Serial PD Matrix*
1
Byte No. Function described
0
1
2
3
4
5
Number of bytes used by
module manufacturer
Total SPD memory size
Memory type
Number of row addresses bits
Number of column
addresses bits
Number of banks
264EN
464EN
6
7
8
9
Module data width
Module data width ( ntinued)
co
Module i terface sgnal levels
n
i
SDRAM cycle time
(highest
CE
latency)
15 ns
SDRAM access from Clock
(highest
CE
latency)
9 ns
Module configuration type
Refresh rate/type
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
80
08
04
0B
09
01
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
02
40
00
01
F0
2
64
0 (+)
LVTTL
CL = 3
128
256 byte
SDRAM
11
9
1
10
1
0
0
1
0
0
0
0
90
11
12
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
80
Non parity
Normal
(15.625
µs)
Self refresh
2M
×
8
—
1 CLK
13
14
15
SDRAM width
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
08
00
01
Error checking SDRAM width 0
0
SDRAM device attributes:
minimum clock delay for
back-to-back random column
addresses
SDRAM device attributes:
Burst lengths supported
1
16
17
0
0
0
0
0
0
1
0
1
0
1
1
1
0
8F
02
1, 2, 4, 8,
full page
2
SDRAM device attributes:
0
number of banks on SDRAM
device
SDRAM device attributes:
CE
latency
SDRAM device attributes:
CS
latency
SDRAM device attributes:
W
latency
SDRAM module attributes
SDRAM device attributes:
General
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
0
1
1
0
0
06
01
01
00
0E
2, 3
0
0
Non buffer
V
CC
±
10%
5