(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[1]
DC Input Voltage
[1]
................................ –0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
[2]
0°C to +70°C
–40°C to +85°C
V
CC
3.3V
±
0.3V
.... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
— TTL Inputs
Automatic CE
Power-Down Current
— CMOS Inputs
GND < V
I
< V
CC
GND < V
OUT
< V
CC
, Output Disabled
V
CC
= Max., f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f=0
Com’l/Ind’l
Com’l
L
Test Conditions
V
CC
= Min.,
I
OH
= –4.0 mA
V
CC
= Min.,
I
OL
= 8.0 mA
2.2
–0.5
–1
–1
7C1041-12V33
Min.
2.4
0.4
V
CC
+ 0.5
0.8
+1
+1
190
40
2.2
–0.5
–1
–1
Max.
7C1041V33-15
Min.
2.4
0.4
V
CC
+ 0.5
0.8
+1
+1
170
40
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB2
8
0.5
8
0.5
mA
mA
Shaded areas contain preliminary information.
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “Instant On” case temperature.
2
CY7C1041V33
Electrical Characteristics
Over the Operating Range (continued)
Test Conditions
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
OUT
< V
CC
,
Output Disabled
V
CC
= Max.,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f=0
Com’l/Ind’l
Com’l
L
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–1
–1
1041V33-17 1041V33-20 1041V33-25
Min. Max. Min.
2.4
0.4
V
CC
+
0.5
0.8
+1
+1
160
40
2.2
–0.5
–1
–1
2.4
0.4
V
CC
+
0.5
0.8
+1
+1
150
40
2.2
–0.5
–1
–1
Max.
Min.
2.4
0.4
V
CC
+
0.5
0.8
+1
+1
130
40
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB2
8
0.5
8
0.5
8
0.5
mA
mA
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= 3.3V
Max.
8
8
Unit
pF
pF
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
3.3V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
1041V33–3
R1 317Ω
THÉVENIN EQUIVALENT
167Ω
OUTPUT
R2
351Ω
1.73V
ALL INPUT PULSES
3.3V
90%
GND
≤
3 ns
10%
90%
10%
≤
3 ns
(b)
1041V33–4
3
CY7C1041V33
Switching Characteristics
[4]
Over the Operating Range
1041V33-12
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[5, 6]
CE LOW to Low Z
[6]
1041V33-15
Min.
15
Max.
1041V33-17
Min.
17
Max.
Unit
ns
17
3
17
8
0
7
3
7
0
17
7
0
8
17
12
12
0
0
12
9
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
12
ns
ns
Description
Min.
12
Max.
12
3
12
6
0
6
3
6
0
12
6
0
6
12
10
10
0
0
10
7
0
3
6
10
12
15
12
12
0
0
12
8
0
3
0
0
3
0
3
15
15
7
7
7
15
7
7
CE HIGH to High Z
[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[5, 6]
Byte Enable to End of Write
WRITE CYCLE
[7, 8]
7
Shaded areas contain preliminary information.
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
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