CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
I
GSS
I
DSS
I
D(ON)
V
GS(TH)
r
DS(ON)
g
fs
t
d(ON)
t
r
t
d(OFF)
t
f
Q
g(TOT)
Q
gs
Q
gd
C
ISS
C
OSS
C
RSS
L
D
Measured from the Drain
Lead, 5mm (0.2in) from
Header to Center of Die
Measured from the
Source Lead, 5mm
(0.2in) from Header to
Source Bonding Pad
Modified MOSFET
Symbol Showing the
Internal Device
Inductances
D
L
D
G
L
S
S
Electrical Specifications
PARAMETER
TEST CONDITIONS
V
GS
= 0V, I
D
= 250µA (Figure 10)
V
GS
=
±20V
V
DS
= Rated BV
DSS
, V
GS
= 0V
V
DS
= 0.8 x Rated BV
DSS
, V
GS
= 0V, T
J
= 125
o
C
V
DS
> I
D(ON)
x r
DS(ON)MAX
, V
GS
= 10V (Figure 7)
V
GS
= V
DS
, I
D
= 250µA
V
GS
= 10V, I
D
= 1.25A (Figures 8, 9)
V
DS
≥
10V, I
D
= 2.0A (Figure 12)
V
DD
= 0.5 x Rated BV
DSS
, I
D
≈
2.5A, R
G
= 9.1Ω,
V
GS
= 10V, R
L
= 78.2Ω For V
DSS
= 200V,
R
L
= 68.2Ω For V
DSS
= 175V (Figures 17, 18),
MOSFET Switching Times are Essentially
Independent of Operating Temperature
V
GS
= 10V, I
D
= 2.5A, V
DS
= 0.8 x Rated BV
DSS
,
I
G(REF)
= 1.5mA (Figures 14, 19, 20) Gate Charge is
Essentially Independent of Operating Temperature
MIN
400
-
-
-
2.5
2.0
-
1.7
-
-
-
-
-
-
-
TYP
-
-
-
-
-
-
1.5
2.2
20
25
50
25
12
6.0
6.0
450
100
20
5.0
MAX
-
±100
25
250
-
4.0
1.800
-
40
50
100
50
15
-
-
-
-
-
-
UNITS
V
nA
µA
µA
A
V
Ω
S
ns
ns
ns
ns
nC
nC
nC
pF
pF
pF
nH
Drain to Source Breakdown Voltage
Gate to Source Leakage Current
Zero-Gate Voltage Drain Current
On-State Drain Current (Note 2)
Gate to Threshold Voltage
Drain to Source On Resistance (Note 2)
Forward Transconductance (Note 2)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
(Gate to Source + Gate to Drain)
Gate to Source Charge
Gate to Drain “Miller” Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Internal Drain Inductance
V
GS
= 0V, V
DS
= 25V, f = 1.0MHz (Figure 11)
-
-
-
-
Internal Source Inductance
L
S
-
15
-
nH
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
θJC
R
θJA
Free Air Operation
-
-
-
-
6.25
175
o
C/W
o
C/W
2
IRFF320
Source to Drain Diode Specifications
PARAMETER
Continuous Source to Drain Current
Pulse Source to Drain Current
(Note 3)
SYMBOL
I
SD
I
SDM
TEST CONDITIONS
Modified MOSFET
Symbol Showing the
Integral Reverse P-N
Junction Rectifier
G
D
MIN
-
-
TYP
-
-
MAX
2.5
10
UNITS
A
A
S
Source to Drain Diode Voltage (Note 2)
Reverse Recovery Time
Reverse Recovered Charge
NOTES:
V
SD
t
rr
Q
RR
T
J
= 25
o
C, I
SD
= 2.5A, V
GS
= 0V (Figure 13)
T
J
= 25
o
C, I
SD
= 2.5A, dI
SD
/d
t
= 100A/µs
T
J
= 25
o
C, I
SD
= 2.5A, dI
SD
/d
t
= 100A/µs
-
-
-
-
450
3.1
1.6
-
-
V
ns
µC
2. Pulse test: pulse width
≤
300µs, duty cycle
≤
2%.
3. Repetitive Rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
