PD - 9.1015
PRELIMINARY
l
l
l
l
l
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IRFBC30S/L
HEXFET
®
Power MOSFET
D
Surface Mount (IRFBC30S)
Low-profile through-hole (IRFBC30L)
Available in Tape & Reel (IRFBC30S)
Dynamic dv/dt Rating
150°C Operating Temperature
Fast Switching
Fully Avalanche Rated
V
DSS
= 600V
R
DS(on)
= 2.2Ω
G
I
D
= 3.6A
S
Description
Third generation HEXFETs from international Rectifier provide the designer with the
best combination of fast switching, ruggedized device design, low on-resistance and
cost-effectiveness.
The D
2
Pak is a surface mount power package capable ofthe accommodatingdie sizes
up to HEX-4. It provides the highest power capability and the lowest possible on-
resistance in any existing surface mount package. The D
2
Pak is suitable for high
current applications because of its low internal connection resistance and can
dissipate up to 2.0W in a typical surface mount application. The through-hole version
(IRFBC30L) is available for low-profile applications.
D 2 Pak
T O -2 6 2
Absolute Maximum Ratings
Parameter
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
A
= 25°C
P
D
@T
C
= 25°C
V
GS
E
AS
I
AR
E
AR
dv/dt
T
J
T
STG
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Power Dissipation
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
3.6
2.3
14
3.1
74
0.59
± 20
290
3.6
7.4
3.0
-55 to + 150
300 (1.6mm from case )
Units
A
W
W
W/°C
V
mJ
A
mJ
V/ns
°C
Thermal Resistance
Parameter
R
θJC
R
θJA
Junction-to-Case
Junction-to-Ambient ( PCB Mounted,steady-state)**
Typ.
–––
–––
Max.
1.7
40
Units
°C/W
7/22/97
IRFBC30S/L
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
V
(BR)DSS
∆V
(BR)DSS
/∆T
J
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
S
C
iss
C
oss
C
rss
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Source Inductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min.
600
–––
–––
2.0
2.5
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.62
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
11
13
35
14
Max. Units
Conditions
–––
V
V
GS
= 0V, I
D
= 250µA
––– V/°C Reference to 25°C, I
D
=1mA
2.2
Ω
V
GS
=10V, I
D
=2.2A
4.0
V
V
DS
= V
GS
, I
D
= 250µA
–––
S
V
DS
= 50V, I
D
= 2.2A
100
V
DS
= 600V, V
GS
= 0V
µA
500
V
DS
= 480V, V
GS
= 0V, T
J
= 125°C
100
V
GS
= 20V
nA
-100
V
GS
= -20V
31
I
D
= 3.6A
4.6
nC
V
DS
= 360V
17
V
GS
= 10V, See Fig. 6 and 13
–––
V
DD
= 300V
–––
I
D
= 3.6A
ns
–––
R
G
= 12Ω
–––
R
D
=82Ω, See Fig. 10
Between lead,
nH
7.5 –––
and center of die contact
660 –––
V
GS
= 0V
86 –––
pF
V
DS
= 25V
19 –––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Notes:
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– –––
3.6
showing the
A
G
integral reverse
––– –––
14
p-n junction diode.
S
––– ––– 1.6
V
T
J
= 25°C, I
S
=3.6A, V
GS
= 0V
––– 370 810
ns
T
J
= 25°C, I
F
=3.6A
––– 2.0 4.2
µC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
V
DD
=50V, starting T
J
= 25°C, L =41mH
R
G
= 25Ω, I
AS
= 3.6A. (See Figure 12)
Pulse width
≤
3000µs; duty cycle
≤
2%.
Uses IRFBC30 data and test conditions
I
SD
≤
3.6A, di/dt
≤
60A/µs, V
DD
≤
V
(BR)DSS
,
T
J
≤
150°C
** When mounted on 1" square PCB (FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
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