PD – 91746C
IRF7805/IRF7805A
HEXFET
®
Chip-Set for DC-DC Converters
•
•
•
•
N Channel Application Specific MOSFETs
Ideal for Mobile DC-DC Converters
Low Conduction Losses
Low Switching Losses
S
S
S
G
1
8
7
A
D
D
D
D
2
3
6
Description
These new devices employ advanced HEXFET Power
MOSFET technology to achieve an unprecedented
balance of on-resistance and gate charge. The
reduced conduction and switching losses make them
ideal for high efficiency DC-DC Converters that power
the latest generation of mobile microprocessors.
The IRF7805/IRF7805A offers maximum efficiency for
mobile CPU core DC-DC converters.
4
5
SO-8
T o p V ie w
Device Features
IRF7805 IRF7805A
Vds
30V
30V
Rds(on)
11mΩ
11mΩ
Qg
31nC
31nC
Qsw
11.5nC
Qoss
36nC
36nC
Absolute Maximum Ratings
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain or Source
Current (V
GS
≥
4.5V)
Pulsed Drain Current
Power Dissipation
25°C
70°C
Junction & Storage Temperature Range
Continuous Source Current (Body Diode)
Pulsed source Current
T
J
, T
STG
I
S
I
SM
2.5
106
25°C
70°C
I
DM
P
D
Symbol
V
DS
V
GS
I
D
13
10
100
2.5
1.6
–55 to 150
2.5
106
°C
A
IRF7805
30
±12
13
10
100
W
A
IRF7805A
Units
V
Thermal Resistance
Parameter
Maximum Junction-to-Ambient
R
θJA
Max.
50
Units
°C/W
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1
10/10/00
IRF7805/IRF7805A
Electrical Characteristics
Parameter
Drain-to-Source
Breakdown Voltage*
Static Drain-Source
on Resistance*
Drain-Source Leakage
Current*
V
(BR)DSS
R
DS
(on)
1.0
30
150
I
GSS
Q
g
Q
gs1
Q
gs2
Q
gd
Q
SW
Q
oss
R
g
t
d
(on)
t
r
t
d
(off)
t
f
±100
22
31
3.7
1.4
6.8
8.2
30
1.7
16
20
38
16
11.5
36
IRF7805
Min Typ Max
30
–
9.2
–
11
1.0
30
150
±100
22
31
3.7
1.4
6.8
8.2
30
1.7
16
20
38
16
ns
36
Ω
V
DD
= 16V
I
D
= 7A
R
g
= 2Ω
V
GS
= 4.5V
Resistive Load
Conditions
I
S
= 7A, V
GS
= 0V
di/dt = 700A/µs
V
DS
= 16V, V
GS
= 0V, I
S
= 7A
di/dt = 700A/µs
(with 10BQ040)
V
DS
= 16V, V
GS
= 0V, I
S
= 7A
V
DS
= 16V, V
GS
= 0
nC
nA
IRF7805A
Min Typ Max Units
30
–
9.2
–
11
V
mΩ
V
µA
Conditions
V
GS
= 0V, I
D
= 250µA
V
GS
= 4.5V, I
D
= 7A
V
DS
= V
GS
,I
D
= 250µA
V
DS
= 24V, V
GS
= 0
V
DS
= 24V, V
GS
= 0,
Tj = 100°C
V
GS
= ±12V
V
GS
= 5V, I
D
= 7A
V
DS
= 16V, I
D
= 7A
Gate Threshold Voltage* V
GS
(th)
I
DSS
Gate-Source Leakage
Current*
Total Gate Charge*
Pre-Vth
Gate-Source Charge
Post-Vth
Gate-Source Charge
Gate to Drain Charge
Switch Charge*
(Q
gs2
+ Q
gd
)
Output Charge*
Gate Resistance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Source-Drain Rating & Characteristics
Parameter
Diode Forward
Voltage*
Reverse Recovery
Charge
Reverse Recovery
Charge (with Parallel
Schotkky)
Notes:
*
Min
V
SD
Q
rr
Q
rr(s)
Typ Max
1.2
88
55
Min
Typ Max Units
1.2
88
55
V
nC
2
Repetitive rating; pulse width limited by max. junction temperature.
Pulse width
≤
300 µs; duty cycle
≤
2%.
When mounted on 1 inch square copper board, t < 10 sec.
Measured at V
DS
< 100mV. This approximates actual operation of a synchronous rectifier.
Typ = measured - Q
oss
Devices are 100% tested to these parameters.
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IRF7805/IRF7805A
Power MOSFET Selection for DC/DC
Converters
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called the
Control FET, are impacted by the R
ds(on)
of the MOSFET,
but these conduction losses are only about one half of
the total losses.
Power losses in the control switch Q1 are given by;
4
Drain Current
1
Gate Voltage
t2
t1
V
GTH
t0
2
t3
Q
GS1
Q
GS2
Q
GD
P
loss
= P
conduction
+ P
switching
+ P
drive
+ P
output
This can be expanded and approximated by;
Drain Voltage
Figure 1: Typical MOSFET switching waveform
P
loss
=
(
I
rms 2
×
R
ds(on)
)
Q
+
I
×
gd
×
V
in
×
i
g
+
(
Q
g
×
V
g
×
f
)
+
Q
oss
×
V
in
×
f
2
Q
f
+
I
×
gs2
×
V
in
×
i
g
f
Synchronous FET
The power loss equation for Q2 is approximated
by;
*
P
loss
=
P
conduction
+
P
drive
+
P
output
P
loss
=
I
rms
×
R
ds(on)
+
(
Q
g
×
V
g
×
f
)
(
2
)
This simplified loss equation includes the terms Q
gs2
and Q
oss
which are new to Power MOSFET data sheets.
Q
gs2
is a sub element of traditional gate-source charge
that is included in all MOSFET data sheets. The impor-
tance of splitting this gate-source charge into two sub
elements, Q
gs1
and Q
gs2
, can be seen from Fig 1.
Q
gs2
indicates the charge that must be supplied by
the gate driver between the time that the threshold volt-
age has been reached (t1) and the time the drain cur-
rent rises to I
dmax
(t2) at which time the drain voltage
begins to change. Minimizing Q
gs2
is a critical factor in
reducing switching losses in Q1.
Q
oss
is the charge that must be supplied to the output
capacitance of the MOSFET during every switching
cycle. Figure 2 shows how Q
oss
is formed by the paral-
lel combination of the voltage dependant (non-linear)
capacitance’s C
ds
and C
dg
when multiplied by the power
supply input buss voltage.
Q
Q
+
oss
×
V
in
×
f
+
(
rr
×
V
in
×
f
)
2
*dissipated primarily in Q1.
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IRF7805/IRF7805A
For the synchronous MOSFET Q2, R
ds(on)
is an im-
portant characteristic; however, once again the impor-
tance of gate charge must not be overlooked since it
impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Q
oss
and re-
verse recovery charge Q
rr
both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and V
in
. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Q
gd
/Q
gs1
must be minimized to reduce the
potential for Cdv/dt turn on.
Spice model for IRF7805 can be downloaded in ma-
chine readable format at www.irf.com.
Figure 2: Q
oss
Characteristic
4
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IRF7805/IRF7805A
Typical Characteristics
IRF7805
IRF7805A
Figure 3. Normalized On-Resistance vs. Temperature
Figure 4. Normalized On-Resistance vs. Temperature
Figure 5. Typical Gate Charge vs. Gate-to-Source Voltage
Figure 6. Typical Gate Charge vs. Gate-to-Source Voltage
Figure 7. Typical Rds(on) vs. Gate-to-Source Voltage
Figure 8. Typical Rds(on) vs. Gate-to-Source Voltage
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