IS61LV12824
128K x 24 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
FEATURES
• High-speed access time: 8, 10 ns
• CMOS low power operation
— 756 mW (max.) operating @ 8 ns
— 36 mW (max.) standby @ 8 ns
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Available in 119-pin Plastic Ball Grid Array
(PBGA) and 100-pin TQFP packages.
• Industrial temperature available
• Lead-free available
ISSI
JUNE 2005
®
DESCRIPTION
The
ISSI
IS61LV12824 is a high-speed, static RAM organized
as 131,072 words by 24 bits. It is fabricated using
ISSI
's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields ac-
cess times as fast as 8 ns with low power consumption.
When
CE1, CE2
are HIGH and CE2 is LOW (deselected), the
device assumes a standby mode at which the power dissipa-
tion can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE1,
CE2,
CE2
and
OE.
The active
LOW Write Enable (WE) controls both writing and reading of
the memory.
The IS61LV12824 is packaged in the JEDEC standard
119-pin PBGA and 100-pin TQFP.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 24
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O23
COLUMN I/O
CE2
CE1
CE2
OE
WE
CONTROL
CIRCUIT
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/22/05
1
IS61LV12824
TRUTH TABLE
Mode
Not Selected
WE
X
X
X
H
H
L
CE1
H
X
X
L
L
L
CE2
X
L
X
H
H
H
CE2
X
X
H
L
L
L
OE
X
X
X
H
L
X
I/O0-I/O23
High-Z
Vcc Current
I
SB
1
, I
SB
2
ISSI
High-Z
D
OUT
D
IN
I
CC
I
CC
I
CC
®
Output Disabled
Read
Write
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
CC
V
TERM
T
STG
T
BIAS
P
T
I
OUT
Parameter
Power Supply Voltage Relative to GND
Terminal Voltage with Respect to GND
Storage Temperature
Temperature Under Bias:
Com.
Ind.
Power Dissipation
DC Output Current
Value
–0.5 to 5.0
–0.5 to Vcc + 0.5
–65 to + 150
–10 to + 85
–45 to + 90
2.0
±20
Unit
V
V
°C
°C
°C
W
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
(8 ns)
3.3V + 10%, – 5%
3.3V + 10%, – 5%
V
CC
(10 ns)
3.3V ± 10%
3.3V ± 10%
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
, Outputs Disabled
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Min.
2.4
—
2.2
–0.3
–1
–1
Max.
—
0.4
V
CC
+ 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
Note:
1. V
IL
(min.) = –0.3V DC; V
IL
(min.) = –2.0V AC (pulse width
≤
2.0 ns).
V
IH
(max.) = V
CC
+ 0.3V DC; V
IH
(max.) = V
CC
+ 2.0V AC (pulse width
≤
2.0 ns).
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/22/05
IS61LV12824
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-8 ns
Symbol
I
CC
I
SB
1
Parameter
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
CC
= Max.,
I
OUT
= 0 mA, f = f
MAX
Com.
Ind.
Min.
Max.
ISSI
-10 ns
Min.
Max.
®
Unit
mA
mA
—
—
—
—
—
—
210
240
70
80
10
20
—
—
—
—
—
—
180
210
50
55
10
20
1
2
V
CC
= Max.,
Com.
V
IN
= V
IH
or V
IL
, f = max.
Ind.
CE1, CE2,
≥
V
IH
, CE2
≤
V
IL
V
CC
= Max.,
Com.
CE1, CE2
≥
V
CC
– 0.2V,
Ind.
CE2
≤
0.2V, V
IN
≥
V
CC
– 0.2V,
or V
IN
≤
0.2V, f = 0
I
SB
2
mA
3
4
5
6
7
8
9
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE
(1)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
2 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
319
Ω
10
11
353
Ω
Z
O
= 50Ω
OUTPUT
50Ω
3.3V
OUTPUT
5 pF
Including
jig and
scope
1.5V
12
Figure 1
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/22/05
5
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