PD - 9.1261D
IRF7601
HEXFET
®
Power MOSFET
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Generation V Technology
Ultra Low On-Resistance
N-Channel MOSFET
Very Small SOIC Package
Low Profile (<1.1mm)
Available in Tape & Reel
Fast Switching
S
S
S
G
1
2
8
7
A
A
D
D
D
D
V
DSS
= 20V
3
4
6
5
R
DS(on)
= 0.035Ω
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
known for, provides the designer with an extremely efficient
and reliable device for use in a wide variety of applications.
The new Micro8 package, with half the footprint area of the
standard SO-8, provides the smallest footprint available in
an SOIC outline. This makes the Micro8 an ideal device for
applications where printed circuit board space is at a
premium. The low profile (<1.1mm) of the Micro8 will allow
it to fit easily into extremely thin application environments
such as portable electronics and PCMCIA cards.
T o p V ie w
Micro8
Absolute Maximum Ratings
Parameter
I
D
@ T
A
= 25°C
I
D
@ T
A
= 70°C
I
DM
P
D
@T
A
= 25°C
V
GS
dv/dt
T
J,
T
STG
Continuous Drain Current, V
GS
@ 4.5V
Continuous Drain Current, V
GS
@ 4.5V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt
Junction and Storage Temperature Range
Max.
5.7
4.6
30
1.8
14
± 12
5.0
-55 to + 150
Units
A
W
mW/°C
V
V/ns
°C
Thermal Resistance
Parameter
R
θJA
Maximum Junction-to-Ambient
Typ.
–––
Max.
70
Units
°C/W
All Micro8 Data Sheets reflect improved Thermal Resistance, Power and Current -Handling Ratings- effective
only for product marked with Date Code 505 or later .
8/25/97
IRF7601
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
V
(BR)DSS
∆V
(BR)DSS
/∆T
J
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
Min.
20
–––
–––
–––
0.70
6.1
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.024
–––
–––
–––
–––
–––
–––
–––
–––
14
2.0
6.3
5.1
47
24
32
650
300
150
Max. Units
Conditions
–––
V
V
GS
= 0V, I
D
= 250µA
––– V/°C Reference to 25°C, I
D
= 1mA
0.035
V
GS
= 4.5V, I
D
= 3.8A
Ω
0.050
V
GS
= 2.7V, I
D
= 1.9A
–––
V
V
DS
= V
GS
, I
D
= 250µA
–––
S
V
DS
= 10V, I
D
= 1.9A
1.0
V
DS
= 16V, V
GS
= 0V
µA
25
V
DS
= 16V, V
GS
= 0V, T
J
= 125°C
-100
V
GS
= -12V
nA
100
V
GS
= 12V
22
I
D
= 3.8A
3.0
nC
V
DS
= 16V
9.5
V
GS
= 4.5V, See Fig. 6 and 9
–––
V
DD
= 10V
–––
I
D
= 3.8A
ns
–––
R
G
= 6.2Ω
–––
R
D
= 2.6Ω, See Fig. 10
–––
V
GS
= 0V
–––
pF
V
DS
= 15V
–––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Min. Typ. Max. Units
–––
–––
–––
–––
–––
–––
–––
–––
51
69
1.8
A
30
1.2
77
100
V
ns
nC
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
T
J
= 25°C, I
S
= 3.8A, V
GS
= 0V
T
J
= 25°C, I
F
= 3.8A
di/dt = 100A/µs
D
G
S
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Pulse width
≤
300µs; duty cycle
≤
2%.
Surface mounted on FR-4 board, t
≤
10sec.
I
SD
≤
3.8A, di/dt
≤
96A/µs, V
DD
≤
V
(BR)DSS
,
T
J
≤
150°C
IRF7601
100
VGS
7.5V
5.0V
4.0V
3.5V
3.0V
2.5V
2.0V
BOTT OM 1.5V
TOP
100
I , D ra in -to -S o u rce C u rre n t (A )
D
10
I , D ra in -to -S o u rce C u rre n t (A )
D
VGS
7.5V
5.0V
4.0V
3.5V
3.0V
2.5V
2.0V
BOTT OM 1.5V
TOP
10
1
1
1.5V
1.5 V
0.1
0.1
1
20 µs P U LSE W IDTH
T
J
= 25 °C
A
10
0.1
0.1
1
20 µs P U LSE W IDTH
T
J
= 15 0°C
A
10
V D S , Drain-to-Source V oltage (V)
V D S , Drain-to-Source V oltage (V)
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
100
2.0
R
D S (on )
, D ra in -to -S o u rce O n R e s is ta n c e
(N o rm a lize d )
I
D
= 3 .8A
I
D
, D r ain- to-S ourc e C urre nt (A )
1.5
10
T
J
= 1 5 0 °C
1.0
T
J
= 2 5 °C
1
0.5
0.1
1.5
2.0
2.5
V
D S
= 1 0 V
2 0 µ s PU L SE W ID TH
3.0
3.5
A
0.0
-60
V
G S
= 4.5 V
-40
-20
0
20
40
60
80
100 120 140 160
A
V
G S
, Ga te-to-S o urce V oltage (V )
T
J
, Junction Temperature (°C )
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
IRF7601
1200
1000
V
G S
, G a te -to -S o u rc e V o lta g e (V )
V
GS
C
iss
C
rs s
C
os s
=
=
=
=
0V ,
f = 1 MH z
C
gs
+ C
gd
, C
ds
SH O R TED
C
gd
C
ds
+ C
gd
10
I
D
= 3.8 A
V
D S
= 16 V
8
C , C a p a c ita n c e (p F )
C
is s
800
C
os s
600
6
4
400
C
rs s
200
2
0
1
10
100
A
0
0
4
8
12
FO R TEST C IR C U IT
SEE F IGU R E 9
16
20
24
A
V
D S
, D rain-to-S ource Voltage (V )
Q
G
, Total Gate Charge (nC)
Fig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage
100
100
I
S D
, R e v e rse D ra in C u rre n t (A )
OPE R ATIO N IN TH IS A RE A LIMITE D
BY R
D S(o n)
10
T
J
= 1 50 °C
T
J
= 25° C
1
I
D
, D ra in C u rre n t (A )
10 0µ s
10
1m s
0.1
0.4
0.8
1.2
1.6
V
G S
= 0 V
2.0
A
1
T
A
= 25 °C
T
J
= 15 0°C
S ing le Pulse
0.1
1
10
10 ms
A
100
2.4
V
S D
, Source-to-D rain V oltage (V )
V
D S
, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 8.
Maximum Safe Operating Area
IRF7601
Q
G
V
DS
V
GS
R
D
4.5V
Q
GS
V
G
Q
GD
D.U.T.
+
R
G
-
V
DD
4.5V
Charge
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 9a.
Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
Fig 10a.
Switching Time Test Circuit
V
DS
50KΩ
12V
.2µF
.3µF
90%
D.U.T.
V
GS
3mA
+
V
-
DS
10%
V
GS
t
d(on)
I
G
I
D
t
r
t
d(off)
t
f
Current Sampling Resistors
Fig 9b.
Gate Charge Test Circuit
100
Fig 10b.
Switching Time Waveforms
D = 0.50
Thermal Response (Z
thJA
)
0.20
10
0.10
0.05
0.02
1
0.01
P
DM
t
1
t
2
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t
1
/ t
2
2. Peak T
J
= P
DM
x Z
thJA
+ T
A
0.01
0.1
1
10
100
0.1
0.00001
0.0001
0.001
t
1
, Rectangular Pulse Duration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
FPGA/CPLD
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