HIGH-SPEED 3.3V
16/8K X 9 DUAL-PORT
STATIC RAM
Features
◆
◆
IDT70V16/5S/L
OBSOLETE PARTS
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial:15/20/25ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V16/5S
Active: 430mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V16/5L
Active: 415mW (typ.)
Standby: 660µW (typ.)
Busy and Interrupt Flag
On-chip port arbitration logic
◆
◆
◆
Functional Block Diagram
OE
L
I/O
0L
- I/O
8L
BUSY
L
A
13L
(1)
A
0L
S OR
T F
R
A D
P E
E D S
T N
E E
L M IGN
O M S
S O
E
B C
D
O E
R EW
T N
O
N
◆
◆
◆
◆
IDT70V16/5 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading more
than one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (+0.3V) power supply
Available in 68-pin PLCC and an 80-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
OE
R
CE
R
R/W
R
CE
L
R/W
L
I/O
0R
-I/O
8R
I/O
Control
I/O
Control
(2,3)
BUSY
R
(2,3)
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
13R
(1)
A
0R
14
14
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(3)
INT
L
NOTES:
1. A
13
is a NC for IDT70V15.
2. In MASTER mode:
BUSY
is an output and is a push-pull driver
In SLAVE mode:
BUSY
is input.
3.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull drivers.
M/S
SEM
R
(3)
INT
R
5669 drw 01
JANUARY 2009
1
©2009 Integrated Device Technology, Inc.
DSC 5669/3
PRELIMINARYPRELIMINARY
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V16/5 is a high-speed 16/8K x 9 Dual-Port Static RAM.
The IDT70V16/5 is designed to be used as stand-alone Dual-Port RAMs
or as a combination MASTER/SLAVE Dual-Port RAM for 18-bit-or-more
wider systems. Using the IDT MASTER/SLAVE Dual-Port RAM ap-
proach in 18-bit or wider memory system applications results in full-speed,
error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by
CE
permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 430mW of power.
The IDT70V16/5 is packaged in a 64-pin PLCC (Plastic Leaded
Chip Carriers) and an 80-pinTQFP (Thin Quad Flatpack).
Pin Configurations
(1,2,3,4)
08/26/02
INDEX
I/O
2L
I/O
3L
I/O
4L
I/O
5L
V
SS
I/O
6L
I/O
7L
V
DD
V
SS
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
9
I/O
1L
I/O
0L
I/O
8L
OE
L
R/W
L
SEM
L
CE
L
N/C
A
13L
(1)
V
DD
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
IDT70V16/5J
J68-1(5)
68-Pin PLCC
Top View(6)
55
54
53
52
51
50
49
48
47
46
45
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
V
SS
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
5669 drw 02
,
NOTES:
1. A
13
is a NC for IDT70V15.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately .95 in x .95 in x .17 in.
5. This package code is used to reference the package diagram.
6. This text does not imply orientation of Part-marking.
I/O
7R
I/O
8R
OE
R
R/W
R
SEM
R
CE
R
N/C
A
13R
(1)
V
SS
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
2
6.42
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3,4)
(con't.)
I/O
1L
I/O
0L
I/O
8L
A
11L
A
12L
CE
L
NC
A
10L
V
DD
A
9L
A
7L
A
8L
A
6L
INDEX
79
78
77
70
69
65
62
72
68
67
76
74
73
80
71
66
64
63
75
61
NC
NC
08/26/02
OE
L
R/W
L
NC
A
13L
(1)
SEM
L
NC
I/O
2L
I/O
3L
I/O
4L
I/O
5L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
60
59
58
57
56
55
54
NC
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
V
SS
I/O
6L
I/O
7L
V
DD
NC
IDT70V16/5PF
PN80-1(5)
80-Pin TQFP
Top View(6)
53
52
51
50
49
48
47
46
45
44
43
42
V
SS
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
NC
NC
V
SS
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
NC
21
27
28
26
30
31
33
34
36
37
38
24
25
29
32
35
39
40
20
22
23
41
I/O
7R
I/O
8R
OE
R
A
13R
(1)
NC
SEM
R
A
11R
A
10R
CE
R
NC
R/W
R
A
12R
A
9R
A
8R
A
7R
A
6R
V
SS
A
5R
NC
NOTES:
1. A
13
is a NC for IDT70V15.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground supply.
4. PN80-1 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
3
6.42
NC
5669 drw 03
PRELIMINARYPRELIMINARY
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
L
R/W
L
OE
L
A
0L
- A
13L
(1)
I/O
0L
- I/O
8L
SEM
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A
0R
- A
13R
(1)
I/O
0R
- I/O
8R
SEM
R
INT
R
BUSY
R
M/S
V
CC
GND
NOTE:
1. A
13
is a NC for IDT70V15.
Right Port
Chip Enable
Names
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power (3.3V)
Ground (0V)
5669 tbl 01
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
CE
H
L
L
X
R/W
X
L
H
X
OE
X
X
L
H
SEM
H
H
H
X
Outputs
I/O
0-8
High-Z
DATA
IN
DATA
OUT
High-Z
Deselcted: Power-Down
Write to Memory
Read Memory
Outputs Disabled
5669 tbl 02
Mode
NOTE:
Condition: A
0L
— A
13L
≠
A
0R
— A
13R
1.
Truth Table II: Semaphore Read/Write Control
(1)
Inputs
CE
H
H
L
R/W
H
↑
X
OE
L
X
X
SEM
L
L
L
Outputs
I/O
0-8
DATA
OUT
DATA
IN
____
Mode
Read Semaphore Flag Data Out (I/O
0
- I/O
8
)
Write I/O
0
into Semaphore Flag
Not Allowed
5669 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from all I/O
s
(I/O
0
-I/O
8
). These eight semaphores are addressed by A
0
- A
2.
4
6.42
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM(2)
T
BIAS(3)
T
STG
T
JN
I
OUT
Rating
Terminal Voltage
with Respect to GND
Temperature Under Bias
Storage Temperature
Junction Temperature
DC Output Current
Commercial
& Industrial
-0.5 to +3.6
-55 to +125
-65 to +150
+150
50
Unit
V
Maximum Operating
Temperature and Supply Voltage
(1)
Grade
Commercial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
3.3V
+
0.3V
3.3V
+
0.3V
5669 tbl 05
o
C
C
C
Industrial
o
o
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
mA
5669 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. V
TERM
must not exceed V
DD
+ 0.3V.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
Recommended DC Operating
Conditions
Symbol
V
DD
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3
(1)
Typ.
3.3
0
____
____
Max.
3.6
0
V
DD
+0.3
(2)
0.8
Unit
V
V
V
V
5669 tbl 06
Capacitance
(1)
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
(2)
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
9
10
Unit
pF
pF
5669 tbl 07
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed V
DD
+ 0.3V.
NOTES:
1. This parameter is determined by device characteristics but is not production
tested.
2. C
OUT
also references C
I/O
.
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(V
DD
= 3.3V ± 0.3V)
70V16/5S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Currentt
(1)
Output Low Voltage
Output High Voltage
Test Conditions
V
DD
= 3.6V, V
IN
= 0V t
o
V
DD
CE
= V
IH
, V
OUT
= 0V t
o
V
DD
I
OL
= +4mA
I
OH
= -4mA
Min.
___
___
___
70V16/5L
Min.
___
___
___
Max.
10
10
0.4
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
5669 tbl 08
2.4
2.4
NOTE:
1. At V
DD
< 2.0V, Input leakages are undefined.
5
6.42
NXP MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
