CMOS SyncFIFO™
64 x 8, 256 x 8, 512 x 8,
1024 x 8, 2048 x 8 and 4096 x 8
Integrated Device Technology, Inc.
IDT72420
IDT72200
IDT72210
IDT72220
IDT72230
IDT72240
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
64 x 8-bit organization (IDT72420)
256 x 8-bit organization (IDT72200)
512 x 8-bit organization (IDT72210)
1024 x 8-bit organization (IDT72220)
2048 x 8-bit organization (IDT72230)
4096 x 8-bit organization (IDT72240)
12 ns read/write cycle time (IDT72420/72200/72210)
15 ns read/write cycle time (IDT72220/72230/72240)
Read and write clocks can be asynchronous or
coincidental
Dual-Ported zero fall-through time architecture
Empty and Full flags signal FIFO status
Almost-empty and almost-full flags set to Empty+7 and
Full-7, respectively
Output enable puts output data bus in high-impedance
state
Produced with advanced submicron CMOS technology
Available in 28-pin 300 mil plastic DIP and 300 mil
ceramic DIP
For surface mount product please see the IDT72421/
72201/72211/72221/72231/72241 data sheet
Military product compliant to MIL-STD-883, Class B
Industrial temperature range (-40
O
C to +85
O
C) is
available, tested to military electrical specifications
DESCRIPTION:
The IDT72420/72200/72210/72220/72230/72240
SyncFIFO™ are very high-speed, low-power First-In, First-
Out (FIFO) memories with clocked read and write controls.
The IDT72420/72200/72210/72220/72230/72240 have a 64,
256, 512, 1024, 2048, and 4096 x 8-bit memory array, respec-
tively. These FIFOs are applicable for a wide variety of data
buffering needs, such as graphics, Local Area Networks
(LANs), and interprocessor communication.
These FIFOs have 8-bit input and output ports. The input
port is controlled by a free-running clock (WCLK), and a write
enable pin (WEN). Data is written into the Synchronous FIFO
on every clock when WEN is asserted. The output port is
controlled by another clock pin (RCLK) and a read enable pin
(REN). The read clock can be tied to the write clock for single
clock operation or the two clocks can run asynchronous of one
another for dual clock operation. An output enable pin (OE) is
provided on the read port for three-state control of the output.
These Synchronous FIFOs have two end-point flags, Empty
(EF) and Full (FF). Two partial flags, Almost-Empty (AE) and
Almost-Full (AF), are provided for improved system control.
The partial ( AE) flags are set to Empty+7 and Full-7 for AE and
AF respectively.
The IDT72420/72200/72210/72220/72230/72240 are fabri-
cated using IDT’s high-speed submicron CMOS technology.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
WCLK
D0 - D7
WEN
•
INPUT REGISTER
FLAG
LOGIC
•
•
RAM ARRAY
64 x 8
256 x 8
512 x 8
•
•
•
WRITE CONTROL
LOGIC
EF
AE
AF
FF
WRITE POINTER
READ POINTER
READ CONTROL
LOGIC
OUTPUT REGISTER
•
RESET LOGIC
RCLK
RS
OE
Q0 - Q7
REN
2680 drw 01
The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
NOVEMBER 1996
DSC-2680/6
5.12
1
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO™
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
D4
D3
D2
D1
D0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DIP TOP
VIEW
P28-2
C28-1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D5
D6
D7
RS
WEN
WCLK
VCC
Q7
Q6
Q5
Q4
Q3
Q2
Q1
2680 drw 02
AF
AE
GND
RCLK
REN
OE
EF
FF
Q0
PIN DESCRIPTIONS
Symbol
D
0
- D
7
Name
Data Inputs
Reset
I/O
I
I
Description
Data inputs for a 8-bit bus.
When
RS
is set LOW, internal read and write pointers are set to the first location of the RAM
array,
FF
and
AF
go HIGH, and
AE
and
EF
go LOW. A reset is required before an initial WRITE
after power-up.
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when
WEN
is asserted.
When
WEN
is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK.
Data will not be written into the FIFO if the
FF
is LOW.
Data outputs for a 8-bit bus.
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when
REN
is asserted.
When
REN
is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the
EF
is LOW.
When
OE
is LOW, the data output bus is active. If
OE
is HIGH, the output data bus will be in a
high-impedance state.
When
EF
is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF
is HIGH, the FIFO is not empty.
EF
is synchronized to RCLK.
When
AE
is LOW, the FIFO is almost empty based on the offset Empty+7.
AE
is synchronized
to RCLK.
When
AF
is LOW, the FIFO is almost full based on the offset Full-7.
WCLK.
RS
WCLK
Write Clock
Write Enable
Data Outputs
Read Clock
Read Enable
Output Enable
Empty Flag
Almost-Empty
Flag
Almost-Full Flag
Full Flag
Power
Ground
I
I
O
I
I
I
O
O
O
O
WEN
Q
0
- Q
7
RCLK
REN
OE
EF
AE
AF
FF
V
CC
GND
AF
is synchronized to
When
FF
is LOW, the FIFO is full and further data writes into the input are inhibited. When
FF
is
HIGH, the FIFO is not full.
FF
is synchronized to WCLK.
One +5 volt power supply pin.
One 0 volt ground pin.
2680 tbl 01
5.12
2
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO™
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Rating
Commercial
Military
–0.5 to + 7.0
Unit
V
Terminal Voltage –0.5 to + 7.0
with Respect to
GND
Operating
0 to + 70
Temperature
Temperature
–55 to + 125
Under Bias
Storage
–55 to + 125
Temperature
DC Output
50
Current
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CCM
V
CCC
GND
V
IH
V
IH
V
IL
Parameter
Military Supply Voltage
Commercial Supply
Voltage
Supply Voltage
Input High Voltage
Commercial
Input High Voltage
Military
Input Low Voltage
Commercial & Military
Min.
4.5
4.5
0
2.0
2.2
—
Typ.
5.0
5.0
0
—
—
—
Max.
5.5
5.5
0
—
—
0.8
Unit
V
V
V
V
V
V
2680 tbl 03
2680 tbl 02
T
A
T
BIAS
T
STG
I
OUT
NOTE:
–55 to + 125
–65 to + 135
–65 to + 135
50
°C
°C
°C
mA
CAPACITANCE
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN (2)
Parameter
Input Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
2680 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
C
OUT(1, 2)
Output Capacitance
NOTES:
1. With output deselected. (
OE
= HIGH)
2. Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5V
±
10%, T
A
= –55°C to +125°C)
IDT72420
IDT72200
IDT72210
Commercial
t
CLK
= 12, 15, 20, 25, 35, 50 ns
Min.
Typ.
Max.
–1
–10
2.4
—
—
—
—
—
—
—
1
10
—
0.4
80
IDT72420
IDT72200
IDT72210
Military
t
CLK
= 20, 25,35, 50 ns
Min.
Typ.
Max.
–10
–10
2.4
—
—
—
—
—
—
—
10
10
—
0.4
100
Symbol
I
LI(1)
I
LO(2)
V
OH
V
OL
I
CC1(3)
Parameter
Input Leakage Current (any input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2 mA
Output Logic “0” Voltage, I
OL
= 8 mA
Active Power Supply Current
Units
µA
µA
V
V
mA
2680 tbl 05
Symbol
I
LI(1)
I
LO(2)
V
OH
V
OL
I
CC1(4)
Parameter
Input Leakage Current (any input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2 mA
Output Logic “0” Voltage, I
OL
= 8 mA
Active Power Supply Current
IDT72220
IDT72230
IDT72240
Commercial
t
CLK
= 15, 20, 25, 35, 50 ns
Min.
Typ.
Max.
–1
–10
2.4
—
—
—
—
—
—
—
1
10
—
0.4
80
IDT72220
IDT72230
IDT72240
Military
t
CLK
= 25, 35, 50 ns
Min.
Typ.
Max.
–10
–10
2.4
—
—
—
—
—
—
—
10
10
—
0.4
100
Units
µA
µA
V
V
mA
2680 tbl 06
NOTES:
1. Measurements with 0.4
≤
V
IN
≤
V
CC
.
2.
OE
≥
V
IH
, 0.4
≤
V
OUT
≤
V
CC
.
3 & 4.
Measurements are made with outputs unloaded. Tested at f
CLK
= 20 MH
Z
.
(3) Typical I
CC1
= 30 + (f
CLK
*0.5/MHz) + (f
CLK
*C
L
*0.02/MHz-pF) mA
(4) Typical I
CC1
= 32 + (f
CLK
*0.6/MHz) + (f
CLK
*C
L
*0.02/MHz-pF) mA
f
CLK
= 1 / t
CLK
C
L
= external capacitive load (30 pF typical)
5.12
3
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO™
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to + 70°C; Military: V
CC
= 5V
±
10%, T
A
= –55°C to +125°C)
Commercial
Comm. & Mil.
72200L12 72200L15 72200L20 72200L25
72210L12 72210L15 72210L20 72210L25
72420L12 72420L15 72420L20 72420L25
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
AF
t
AE
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Set-up Time
Data Hold Time
Enable Set-up Time
Enable Hold Time
Reset Pulse
Width
(1)
Reset Set-up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z
(2)
Output Enable to Output Valid
Output Enable to Output in High-Z
(2)
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Almost-Full Flag
Read Clock to Almost-Empty Flag
— 83.3
2
12
5
5
3
0.5
3
0.5
12
12
12
—
0
3
3
—
—
—
—
5
22
8
—
—
—
—
—
—
—
—
—
—
12
—
7
7
8
8
8
8
—
—
— 66.7
2
15
6
6
4
1
4
1
15
15
15
—
0
3
3
—
—
—
—
6
28
10
—
—
—
—
—
—
—
—
—
—
15
—
8
8
10
10
10
10
—
—
—
2
20
8
8
5
1
5
1
20
20
20
—
0
3
3
—
—
—
—
8
35
50
12
—
—
—
—
—
—
—
—
—
—
20
—
10
10
12
12
12
12
—
—
—
3
25
10
10
6
1
6
1
25
25
25
—
0
3
3
—
—
—
—
10
40
40
15
—
—
—
—
—
—
—
—
—
—
25
—
13
13
15
15
15
15
—
—
Comm.
72200L35
72210L35
72420L35
— 28.6
3
35
14
14
8
2
8
2
35
35
35
—
0
3
3
—
—
—
—
12
42
20
—
—
—
—
—
—
—
—
—
—
35
—
15
15
20
20
20
20
—
—
Comm/Mil
72200L50
72210L50
72420L50
Min.Max. Unit
— 20
3
25
50 —
20 —
20 —
10 —
2
2
—
—
10 —
50 —
50 —
50 —
— 50
0
3
3
—
28
28
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
— 30
— 30
— 30
— 30
15 —
45 —
t
SKEW1
Skew time between Read Clock &
Write Clock for Empty Flag & Full Flag
t
SKEW2
Skew time between Read Clock &
Write Clock for Almost-Empty Flag &
Almost-Full Flag
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
2680 tbl 07
5.12
4
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO™
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to + 70°C; Military: V
CC
= 5V
±
10%, T
A
= –55°C to +125°C)
Commercial
72220L12
72220L15
72230L12
72230L15
72240L12
72240L15
Min. Max. Min. Max.
—
2
12
5
5
3
.5
3
.5
(1)
Symbol Parameter
fS
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tRS
tRSS
tRSR
tRSF
tOLZ
tOE
tOHZ
tWFF
tREF
tAF
tAE
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Set-up Time
Data Hold Time
Enable Set-up Time
Enable Hold Time
Reset Pulse Width
Commercial & Military
72220L20
72220L25
72230L20
72230L25
72240L20
72240L25
Min. Max. Min. Max.
—
2
20
8
8
5
1
5
1
20
20
20
—
0
3
3
—
—
—
—
8
50
12
—
—
—
—
—
—
—
—
—
—
20
—
10
10
12
12
12
12
—
—
3
25
10
10
6
1
6
1
25
25
25
—
0
3
3
—
—
—
—
10
40
15
—
—
—
—
—
—
—
—
—
—
25
—
13
13
15
15
15
15
—
Comm.
72220L35
72230L35
72240L35
Min. Max.
—
3
35
14
14
8
2
8
2
35
35
35
—
0
3
3
—
—
—
—
12
28.6
20
—
—
—
—
—
—
—
—
—
—
35
—
15
15
20
20
20
20
—
Comm./Mil.
72220L50
72230L50
72240L50
Min. Max.
—
3
50
20
20
10
2
10
2
50
50
50
—
0
3
3
—
—
—
—
15
20
25
—
—
—
—
—
—
—
—
—
—
50
—
23
23
30
30
30
30
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
83.3
8
—
—
—
—
—
—
—
—
—
—
12
—
7
7
8
8
8
8
—
—
2
15
6
6
4
1
4
1
15
15
15
—
0
3
3
—
—
—
—
6
66.7
10
—
—
—
—
—
—
—
—
—
—
15
—
8
8
10
10
10
10
—
12
12
12
—
0
3
(2)
Reset Set-up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z
(2)
Output Enable to Output Valid
Output Enable to Output in High-Z
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Almost-Full Flag
Read Clock to Almost-Empty Flag
3
—
—
—
—
5
tSKEW1 Skew time between Read Clock
& Write Clock for Empty Flag &
Full Flag
tSKEW2 Skew time between Read Clock &
Write Clock for Almost-Empty Flag
& Almost-Full Flag
22
—
28
—
35
—
40
—
42
—
45
—
ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
2680 tbl 08
5V
1.1K
Ω
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
2680 tbl 09
D.U.T.
680
Ω
30pF*
2680 drw 03
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
5.12
5
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
