CAT25010, CAT25020, CAT25040
1K/2K/4K SPI Serial CMOS EEPROM
FEATURES
I
10 MHz SPI compatible
I
1.8 to 5.5 volt operation
I
SPI modes (00 & 11)
I
16-byte page write buffer
I
Self-timed write cycle
I
Hardware and software protection
I
Block write protection
DESCRIPTION
The CAT25010/20/40 is a 1K/2K/4K Bit SPI Serial
CMOS EEPROM internally organized as 128x8/256x8/
512x8 bits. Catalyst’s advanced CMOS Technology
substantially reduces device power requirements. The
CAT25010/20/40 features a 16-byte page write buffer.
The device operates via the SPI bus serial interface and
is enabled though a Chip Select (CS). The
HOLD
pin
may be used to suspend any serial communication
without resetting the serial sequence. The CAT25010/
20/40 is designed with software and hardware write
protection features including Block Write protection.
– Protect 1/4, 1/2 or all of EEPROM array
I
Low power CMOS technology
I
1,000,000 program/erase cycles
I
100 year data retention
I
Industrial temperature range
I
RoHS-compliant 8-lead PDIP, SOIC, TSSOP
and 8-pad TDFN packages.
For Ordering Information details, see page 17.
PIN CONFIGURATION
PDIP (L)
SOIC (V)
TSSOP (Y)
TDFN (VP2)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
FUNCTIONAL SYMBOL
VCC
SI
CS
WP
HOLD
SCK
CAT25010
CAT25020
CAT25040
SO
PIN FUNCTIONS
Pin Name
SO
SCK
WP
V
CC
V
SS
CS
SI
HOLD
Function
Serial Data Output
Serial Clock
Write Protect
+1.8V to +5.5V Power Supply
Ground
Chip Select
Serial Data Input
Suspends Serial Input
VSS
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1006, Rev. S
CAT25010, CAT25020, CAT25040
ABSOLUTE MAXIMUM RATINGS
(1)
Storage Temperature
Voltage on Any Pin with Respect to Ground
(2)
RELIABILITY CHARACTERISTICS
(3)
Symbol
N
END(4)
T
DR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
-65°C to +150°C
-0.5 V to +6.5 V
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
I
CC
I
SB1
I
SB2
I
L
I
LO
V
IL
V
IH
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Supply Current
Standby Current
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
CC
> 2.5V, I
OL
= 3.0mA
V
CC
> 2.5V, I
OH
= -1.6mA
V
CC
> 1.8V, I
OL
= 150µA
V
CC
> 1.8V, I
OH
= -100µA
V
CC
- 0.2V
V
CC
- 0.8V
0.2
Test Conditions
Read, Write, V
CC
= 5.0V, f
SCK
= 10MHz,
SO open
V
IN
= GND or V
CC
,
CS =
V
CC
,
WP =
V
CC
,
V
CC
= 5V
V
IN
= GND or V
CC
,
CS =
V
CC
,
WP =
GND,
V
CC
= 5V
V
IN
= GND or V
CC
CS =
V
CC
, V
OUT
= GND or V
CC
-2
-1
-0.5
0.7V
CC
Min
Max
2
2
4
2
1
0.3V
CC
V
CC
+ 0.5
0.4
Units
mA
µA
µA
µA
µA
V
V
V
V
V
V
PIN CAPACITANCE
(3)
T
A
= 25°C, f = 1 MHz, V
CC
= 5V
Symbol
C
OUT
C
IN
Test Conditions
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI,
WP, HOLD)
Max
8
6
Conditions
V
OUT
= 0 V
V
IN
= 0 V
Units
pF
pF
Note:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than V
CC
+ 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than V
CC
+ 1.5V, for periods of less than 20ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, V
CC
= 5 V, 25°C
Doc. No. 1006, Rev. S
2
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25010, CAT25020, CAT25040
A.C. CHARACTERISTICS
T
A
= -40°C to +85°C, unless otherwise specified.
(1)
V
CC
= 1.8V-5.5V
SYMBOL PARAMETER
t
SU
t
H
t
WH
t
WL
f
SCK
t
LZ
t
RI(2)
t
FI(2)
t
HD
t
CD
t
WC(4)
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
WPS
t
WPH
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
HOLD
to Output Low Z
Input Rise Time
Input Fall Time
HOLD
Setup Time
HOLD
Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD
to Output High Z
CS
High Time
CS
Setup Time
CS
Hold Time
WP
Setup Time
WP
Hold Time
50
50
50
10
10
0
50
100
15
15
15
10
10
0
10
5
75
0
20
25
Min.
30
30
75
75
DC
5
50
2
2
0
10
5
40
Max.
V
CC
= 2.5V-5.5V
Min.
20
20
40
40
DC
10
25
2
2
Max.
UNITS
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
Power-Up Timing
(2)(3)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
1
1
Units
ms
ms
NOTE:
(1) AC Test Conditions:
Input Pulse Voltages: 0.3V
CC
to 0.7V
CC
Input rise and fall times:
≤10ns
Input and output reference voltages: 0.5V
CC
Output load: current source IOL max/IOH max; C
L
=50pF
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
(4) t
WC
is the time from the rising edge of
CS
after a valid write sequence to the end of the internal write cycle.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1006, Rev. S
CAT25010, CAT25020, CAT25040
FUNCTIONAL DESCRIPTION
The CAT25010/20/40 supports the SPI bus data
transmission protocol. The synchronous Serial Peripheral
Interface (SPI) helps the CAT25010/20/40 to interface
directly with many of today’s popular microcontrollers.
The CAT25010/20/40 contains an 8-bit instruction
register. (The instruction set and the operation codes
are detailed in the instruction set table)
After the device is selected with
CS
going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
PIN DESCRIPTION
SI:
Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
CAT25010/20/40. Input data is latched on the rising
edge of the serial clock for SPI modes (0, 0 & 1, 1).
SO:
Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT25010/20/40. During a read
cycle, data is shifted out on the falling edge of the serial
clock for SPI modes (0,0 & 1,1).
Figure 1. Sychronous Data Timing
V
IH
t
CS
CS
V
IL
t
CSS
V
IH
t
CSH
SCK
V
IL
t
SU
V
IH
t
WH
t
H
t
WL
SI
VIL
VALID IN
t
RI
tFI
t
V
t
HO
t
DIS
HI-Z
V
OH
SO
V
OL
HI-Z
Note: Dashed Line= mode (1, 1) – – – – –
INSTRUCTION SET
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 X011
(1)
0000 X010
(1)
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
Note:
(1) X=0 for CAT25010, CAT25020. X=A8 for CAT25040
Doc. No. 1006, Rev. S
4
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25010, CAT25020, CAT25040
WP:
WP
Write Protect
WP
is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When
WP
is tied low all write operations are inhibited.
WP
held low while
CS
is low will interrupt a write to the
CAT25010/20/40. If the internal write cycle has already
been initiated,
WP
going low will have no effect on any
write operation. Figure 10 illustrates the
WP
timing
sequence during a write operation.
HOLD
Hold
HOLD:
The
HOLD
pin is used to pause transmission to the
CAT25010/20/40 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause,
HOLD
must be brought low while SCK
is low. The SO pin is in a high impedance state during
the time the part is paused, and transitions on the SI pins
will be ignored. To resume communication,
HOLD
is
brought high, while SCK is low. (HOLD should be held
high any time this function is not being used.)
HOLD
may
be tied high directly to V
CC
or tied to V
CC
through a
resistor. Figure 9 illustrates hold timing sequence.
SCK:
Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT25010/20/40. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge
of the SCK for SPI modes (0,0 & 1,1) .
CS:
CS
Chip Select
CS
is the Chip select pin.
CS
low enables the CAT25010/
20/40 and
CS
high disables the CAT25010/20/40.
CS
high takes the SO output pin to high impedance and
forces the devices into a Standby Mode (unless an
internal write operation is underway). A high to low
transition on
CS
is required prior to any sequence being
initiated. A low to high transition on
CS
after a valid write
sequence is what initiates an internal write cycle.
STATUS REGISTER
7
1
6
1
5
1
4
1
3
BP1
2
BP0
1
WEL
0
RDY
BLOCK PROTECTION BITS
Status Register Bits
BP1
BP0
0
0
0
1
Array Address
Protected
None
CAT25010: 60-7F
CAT25020: C0-FF
CAT25040: 180-1FF
CAT25010: 40-7F
CAT25020: 80-FF
CAT25040: 100-1FF
CAT25010: 00-7F
CAT25020: 00-FF
CAT25040: 000-1FF
Protection
No Protection
Quarter Array Protection
1
0
Half Array Protection
1
1
Full Array Protection
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1006, Rev. S
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
