IS41C16128
IS41C16128
128K x 16 (2-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
DESCRIPTION
ISSI
ISSI
®
®
AUGUST 1998
FEATURES
• Extended Data-Out (EDO) Page Mode
access cycle
• TTL compatible inputs and outputs
• Refresh Interval: 512 cycles/8 ms
• Refresh Mode :
RAS
-Only,
CAS
-before-
RAS
(CBR), and Hidden
• JEDEC standard pinout
• Single +5V
±
10% power supply
• Byte Write and Byte Read operation via two
CAS
• Available in 40-pin SOJ and TSOP (Type II)
• Industrial temperature available
The
ISSI
IS41C16128 is a 131,072 x 16-bit high-performance
CMOS Dynamic Random Access Memory. The IS41C16128
offers an accelerated cycle access called EDO Page Mode.
EDO Page Mode allows 256 random accesses within a
single row with access cycle time as short as 12 ns per 16-
bit word. The Byte Write control, of upper and lower byte,
makes the IS41C16128 ideal for use in 16-, 32-bit wide data
bus systems.
These features make the IS41C16128 ideally suited for
high band-width graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
The IS41C16128 is packaged in a 40-pin 400-mil SOJ and
TSOP (Type II).
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
OE
CAS
WE
RAS
RAS
CLOCK
GENERATOR
DATA I/O BUS
REFRESH
COUNTER
DATA I/O BUFFERS
ROW DECODER
RAS
COLUMN DECODERS
SENSE AMPLIFIERS
I/O0-I/O15
MEMORY ARRAY
131,072 x 16
ADDRESS
BUFFERS
A0-A8
This document contains PRELIMINARY data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We
assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
PRELIMINARY
DR002-1D
08/20/98
1
IS41C16128
Functional Description
The IS41C16128 is a CMOS DRAM optimized for high-
speed bandwidth, low power applications. During READ
or WRITE cycles, each bit is uniquely addressed through
the 17 address bits. The row address is latched by the
Row Address Strobe (
RAS
). The column address is
latched by the Column Address Strobe (
CAS
).
RAS
is
used to latch the first nine bits and
CAS
is used to latch the
latter nine bits.
The IS41C16128 has two
CAS
controls,
LCAS
and
UCAS
.
The
LCAS
and
UCAS
inputs internally generates a
CAS
signal functioning in an identical manner to the single
CAS
input on the other 128K x 16 DRAMs. The key difference
is that each
CAS
controls its corresponding I/O tristate
logic (in conjunction with
OE
and
WE
and
RAS
).
LCAS
controls I/O0 through I/O7 and
UCAS
controls I/O8
through I/O15.
The IS41C16128
CAS
function is determined by the first
CAS
(
LCAS
or
UCAS
) transitioning LOW and the last
transitioning back HIGH. The two
CAS
controls give the
IS41C16128 both BYTE READ and BYTE WRITE cycle
capabilities.
ISSI
Refresh Cycle
®
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory.
1. By clocking each of the 512 row addresses (A0 through
A8) with
RAS
at least once every 8 ms. Any read, write,
read-modify-write or
RAS
-only cycle refreshes the ad-
dressed row.
2. Using a
CAS
-before-
RAS
refresh cycle.
CAS
-before-
RAS
refresh is activated by the falling edge of
RAS
,
while holding
CAS
LOW. In
CAS
-before-
RAS
refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS
-before-
RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 256 columns within
a selected row to be randomly accessed at a high data
rate.
In EDO page mode read cycle, the data-out is held to the
next
CAS
cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the
CAS
cycle time becomes shorter. There-
fore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the
CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS
cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one
RAS
cycle, but the performance is
equivalent to that of the fast page mode in that case.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE
,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time speci-
fied by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
,
t
CAC
and t
OEA
are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
Power-On
After application of the V
CC
supply, an initial pause of
200
µs
is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE
,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS
or
WE
, whichever occurs
last.
4
Integrated Silicon Solution, Inc.
PRELIMINARY
DR002-1D
08/20/98
微控制器 MCU
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