FemtoClock Jitter Attenuator & Frequency
Translator w/LVDS Outputs
®
ICS814253
DATA SHEET
General Description
The ICS814253 is a PLL based synchronous clock generator that is
optimized for Gigabit Ethernet and PCI Express™ clock jitter
attenuation and frequency translation. The device contains two
internal frequency multiplication stages that are cascaded in series.
The first stage is a VCXO PLL that is optimized to provide reference
clock jitter attenuation. The second stage is a FemtoClock®
frequency multiplier that provides the low jitter, high frequency
Gigabit Ethernet or PCI-Express output clock.
Pre-divider and output divider multiplication ratios are selected using
device selection control pins. The multiplication ratios are optimized
to support most common clock rates used in Gigabit Ethernet and
PCI-Express applications. The VCXO requires the use of an external,
inexpensive pullable crystal. The VCXO uses external passive loop
filter components which allows configuration of the PLL loop
bandwidth and damping characteristics.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Three differential LVDS output pairs
One differential input supports the following input types: LVPECL,
LVDS, LVHSTL, HCSL
Accepts input frequencies from 19.6MHz to 136MHz, including:
25MHz, 62.5MHz, 100MHz and 125MHz input clocks
Attenuates the phase jitter of the input clock by using a low-cost
fundamental mode VCXO crystal
Outputs common Gigabit Ethernet or PCI Express clock rates
VCXO PLL bandwidth can be optimized for jitter attenuation and
reference tracking using external loop filter connection
Absolute pull range: ±50ppm
FemtoClock frequency multiplier provides low jitter,
high frequency output
FemtoClock VCO range: 490MHz - 680MHz
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.407ps (typical)
Full 3.3V supply, or mixed 3.3V core/2.5V output supply
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
ICS814253
24 Lead TSSOP
4.4mm x 7.85mm x 0.925mm
package body
G Package
Top View
LF
V
DDA
V
DD
V
DDO
nQ0
Q0
PSEL0
GND
PSEL1
XTAL_OUT
XTAL_IN
GND
Block Diagram
LF External
Loop Filter Input
nBypass
Pullup
XTAL_OUT
XTAL_IN
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
V
DDO
nQ2
Q2
nQ1
Q1
FSEL0
GND
FSEL1
nBYPASS
CLK
nCLK
Q0
Pulldown
0
Pre-Divider
1, 2.5,
4, 5
Phase
Detector
VCXO
FemtoClock
Frequency
Multiplier x25
1
CLK1
nCLK1
Pullup/Pulldown
Output
Divider
2, 4, 5, 25
nQ0
Q1
nQ1
Q2
PSEL0
Pullup
PSEL1
Pullup
FSEL0
Pullup
FSEL1
Pullup
OE
Pullup
VCXO Jitter Attenuation PLL
nQ2
ICS814253BG
REVISION A APRIL 18, 2012
1
©2012 Integrated Device Technology, Inc.
ICS814253 Data Sheet
FEMTOCLOCK
®
JTTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVDS OUTPUTS
Table 1. Pin Descriptions
Number
1
2
3
4, 23
5, 6
7,
9
8, 12, 17
10,
11
13
14
15
16,
18
19, 20
21, 22
24
Name
LF
V
DDA
V
DD
V
DDO
nQ0, Q0
PSEL0,
PSEL1
GND
XTAL_OUT,
XTAL_IN
nCLK
CLK
nBypass
FSEL1,
FSEL0
Q1, nQ1
Q2, nQ2
OE
Type
Analog
Input/Output
Power
Power
Power
Output
Input
Power
Input
Input
Input
Input
Input
Output
Output
Input
Pullup
Pullup/
Pulldown
Pulldown
Pullup
Pullup
Pullup
Description
Loop filter connection node pin.
Analog supply pin.
Core supply pin.
Output power supply pins.
Differential clock outputs. LVDS interface levels.
Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A.
Power supply ground.
VCXO crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the
output.
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
Non-inverting differential clock input.
PLL Bypass control pin. See Table 3D.
Select pins. See Table 3B.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Output enable. LVCMOS/LVTTL interface levels. See Table 3C.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
Function Tables
Table 3A. Pre-divider Selection Function Table
Inputs
PSEL1
0
0
1
1
PSEL0
0
1
0
1
Pre-Divider Value
÷1
÷2.5
÷4
÷5 (default)
FSEL1
0
0
1
1
Table 3B. FSEL Function Table
Inputs
FSEL0
0
1
0
1
Output Divider Value
÷2
÷4
÷5
÷25 (default)
ICS814253BG REVISION A APRIL 18, 2012
2
©2012 Integrated Device Technology, Inc.
ICS814253 Data Sheet
FEMTOCLOCK
®
JTTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVDS OUTPUTS
Table 3C. OE Function Table
Input
OE
0
1
Q[0:2]
LOW
Enabled
Clock Outputs
nQ[0:2]
HIGH
Enabled (default)
Table 3D. Bypass Function Table
nBypass Input
0
1 (default)
Operation
VCXO jitter attenuation PLL and FemtoClock multiplier bypassed. Input passed directly to the output divider.
Normal operation mode.
Table 3E. Example Frequency Function Table
Input
Frequency
(MHz)
25
25
25
25
62.5
62.5
62.5
62.5
100
100
100
100
100
100
100
100
125
125
125
125
Input
Divider
÷1
÷1
÷1
÷1
÷2.5
÷2.5
÷2.5
÷2.5
÷4
÷4
÷4
÷4
÷5
÷5
÷5
÷5
÷5
÷5
÷5
÷5
VCXO Crystal
Frequency
(MHz)
25
25
25
25
25
25
25
25
25
25
25
25
20
20
20
20
25
25
25
25
FemtoClock
VCO Frequency
(MHz)
625
625
625
625
625
625
625
625
625
625
625
625
500
500
500
500
625
625
625
625
Output
Divider
Value
÷2
÷4
÷5
÷25
÷2
÷4
÷5
÷25
÷2
÷4
÷5
÷25
÷2
÷4
÷5
÷25
÷2
÷4
÷5
÷25
Output
Frequency
(MHz)
312.5
156.25
125
25
312.5
156.25
125
25
312.5
156.25
125
25
250
125
100
20
312.5
156.25
125
25
PSEL1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
PSEL0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
FSEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FSEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ICS814253BG
REVISION A APRIL 18, 2012
3
©2012 Integrated Device Technology, Inc.
ICS814253 Data Sheet
FEMTOCLOCK
®
JTTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVDS OUTPUTS
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
82.3°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.13
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
113
13
66
Units
V
V
V
mA
mA
mA
Table 4B. LVDS Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.13
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
V
DD
2.625
113
13
64
Units
V
V
V
mA
mA
mA
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
OE, PSEL[1:0],
nBypass, FSEL[1:0]
OE, PSEL[1:0],
nBypass, FSEL[1:0]
V
DD
= V
IN
= 3.465V
V
DD
= 3.465, V
IN
= 0V
4
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
Units
V
V
µA
µA
©2012 Integrated Device Technology, Inc.
ICS814253BG REVISION A APRIL 18, 2012
ICS814253 Data Sheet
FEMTOCLOCK
®
JTTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVDS OUTPUTS
Table 4C. Differential DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
nCLK
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
CLK, nCLK
CLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.15
GND + 0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2. Common mode voltage is defined as V
IH.
Table 4D. DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 3.3V ± 5% or 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.25
Test Conditions
Minimum
247
Typical
Maximum
525
50
1.55
50
Units
mV
mV
V
mV
ICS814253BG
REVISION A APRIL 18, 2012
5
©2012 Integrated Device Technology, Inc.
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