ILX526A
3000-pixel CCD Linear Image Sensor (B/W)
Description
The ILX526A is a rectangular reduction type CCD
linear image sensor designed for bar code POS
hand scanner and optical measuring equipment use.
A built-in timing generator and clock-drivers ensure
single 5V power supply for easy use.
Features
•
•
•
•
Number of effective pixels: 3000 pixels
Pixel size: 7µm
×
200µm (7µm pitch)
Single 5V power supply
High sensitivity: 300V/(lx · s)
22 pin DIP (Cer-DIP)
Internal Structure
Readout gate pulse
generator
Shutter pulse
generator
•
Built-in timing generator and clock-drivers
•
Built-in sample-and-hold circuit
•
Electrical shutter function
•
Clock frequency: 100kHz (Min), 1MHz (Max)
Absolute Maximum Ratings
•
Supply voltage
V
DD
•
Operating temperature
•
Storage temperature
GND
8
V
DD
9
Clock pulse
generator
V
DD
14
CCD analog shift register
Readout gate
Clock-drivers
Clock-drivers
Pin Configuration
(Top View)
V
DD
22
Readout gate
CCD analog shift register
Vgg 1
φCLK
2
NC 3
NC 4
NC 5
φROG
6
φSHUT
7
GND 8
V
DD
9
T1 10
NC 11
3000
1
22 V
DD
21
21 GND
20 V
OUT
19 NC
18 NC
17 NC
16 NC
15 NC
GND
Vgg
13 GND
12 S/HSW
Output Amplifier
S/H circuit
14 V
DD
1
10
12
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
V
OUT
20
E97803-PS
S/HSW
T1
φCLK
S2999
S3000
D56
2
D54
D55
S1
S2
S3
D24
D25
D65
6
–10 to +60
–30 to +80
V
°C
°C
GND
13
φROG
6
φSHUT
7
ILX526A
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Symbol
Vgg
φCLK
NC
NC
NC
φROG
φSHUT
GND
V
DD
T1
NC
S/HSW
GND
V
DD
NC
NC
NC
NC
NC
V
OUT
GND
V
DD
Output circuit gate bias
Clock pulse input
NC
NC
NC
Readout gate pulse input
Electrical Shutter pulse input
GND
5V
TEST
NC
Switch (with S/H or without S/H)
GND
5V
NC
NC
NC
NC
NC
Signal output
GND
5V
Description
Mode Description
Mode in Use
With S/H
Without S/H
12 pin S/HSW
GND
V
DD
Recommended Voltage
Item
V
DD
Min.
4.5
Typ.
5.0
Max.
5.5
Unit
V
Input Pin Capacity
Item
Input capacity of
φCLK
pin
Input capacity of
φROG
pin
Input capacity of
φSHUT
pin
Symbol
Cφ
CLK
Cφ
ROG
Cφ
ROG
Min.
—
—
—
–2–
Typ.
10
10
10
Max.
—
—
—
Unit
pF
pF
pF
ILX526A
Electro-optical Characteristics
(Note 1)
Ta = 25°C, V
DD
= 5V, Clock frequency: 500kHz, Light source = 3200K,
IR cut filter: CM-500S (t = 1.0mm), Without S/H mode
Item
Sensitivity 1
Sensitivity 2
Sensitivity nonuniformity
Saturation output voltage
Dark voltage average
Dark signal nonuniformity
Image lag
Dynamic range
Saturation exposure
5V current consumption
Total transfer efficiency
Output impedance
Offset level
Symbol
R1
R2
PRNU
V
SAT
V
DRK
DSNU
IL
DR
SE
I
VDD
TTE
Z
O
V
OS
Min.
210
—
—
0.6
—
—
—
—
—
—
92.0
—
—
Typ.
300
3700
5.0
0.8
2.5
5.0
5.0
320
0.003
7.0
97.0
250
2.5
Max.
390
—
10.0
—
6.0
12.0
—
—
—
17.0
—
—
—
Unit
V/(lx · s)
V/(lx · s)
%
V
mV
mV
%
—
lx · s
mA
%
Ω
V
Remarks
Note 2
Note 3
Note 4
—
Note 5
Note 6
Note 7
Note 8
Note 9
—
—
—
Note 10
Note)
1. In accordance with the given electrooptical characteristics, the even black level is defined as the average
value of D24, D26 to D52. The odd black level is defined as the average value of D25 , D27 to D53.
2. For the sensitivity test light is applied with a uniform intensity of illumination.
3. Light source: LED
λ
= 660nm
4. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.
PRNU =
(V
MAX
– V
MIN
)/2
V
AVE
×
100 [%]
5.
6.
7.
8.
Where the 3000 pixels are divided into blocks of even and odd pixels, respectively, the maximum output of
each block is set to V
MAX
, the minimum output to V
MIN
and the average output to V
AVE
.
Integration time is 10ms.
The difference between the maximum and average values of the dark output voltage is calculated for even
and odd respectively. Integration time is 10ms.
Typical value is used for clock pulse and readout pulse. V
OUT
= 500mV.
V
SAT
DR =
V
DRK
When optical integration time is shorter, the dynamic range sets wider because dark voltage is in
proportion to optical integration time.
V
SAT
9.
SE = R1
10. Vos is defined as indicated below.
V
OUT
D51
D52
D53
D54
D55
S1
V
OS
GND
–3–
Clock Timing Diagram (With S/H mode)
5
φROG
0
5
φSHUT
0
0
1
5
φCLK
0
–1
2
D1
D23
S1
S2
D3
D53
S4
D21
S2998
D56
D61
D55
S2999
D64
D58
D60
D57
D59
D62
D0
D2
D24
D4
D22
D54
S3
S2997
S3000
V
OUT
Optical black
(30 pixels)
Dummy signal (55 pixels)
Effective picture
elements signal
(3000 pixels)
Dummy signal
(10 pixels)
1-Line output period (3066 pixels)
3100 or more clock pulses are required.
D63
D65
–4–
ILX526A
Clock Timing Diagram (Without S/H mode)
5
φROG
0
5
φSHUT
0
2
0
5
φCLK
0
–1
1
S2997
D57
D59
D23
S1
D2
S2
D61
D63
D56
D52
D21
S2998
D4
D53
D55
S2999
D64
D58
D60
D0
D1
D24
D3
D22
S3
D54
V
OUT
Optical black
(30 pixels)
Dummy signal (55 pixels)
S3000
Effective picture
elements signal
(3000 pixels)
Dummy signal
(10 pixels)
1-Line output period (3066 pixels)
3100 or more clock pulses are required.
D62
D65
–5–
ILX526A
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