329
PRELIMINARY
CY7C1360V25
CY7C1362V25
CY7C1364V25
256K x 36/256K x 32/512K x 18 Pipelined SRAM
Features
• Supports 200-MHz bus
• Fully registered inputs and outputs for pipelined
operation
• Single 2.5V power supply
• Fast clock-to-output times
— 3.1 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device
— 5.0 ns (for 100-MHz device
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Available as a 100-pin TQFP or 119 BGA
• “ZZ” Sleep Mode option and Stop Clock option
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 3.1 ns (200-MHz
device).
The CY7C1360V25/CY7C1364V25/CY7C1362V25 supports
either the interleaved burst sequence used by the Intel Pen-
tium processor or a linear burst sequence used by processors
such as the PowerPC™. The burst sequence is selected
through the MODE pin. Accesses can be initiated by assert-
ing either the Processor Address Strobe (ADSP) or the Con-
troller Address Strobe (ADSC) at clock rise. Address advance-
ment through the burst sequence is controlled by the ADV
input. A 2-bit on-chip wraparound burst counter captures the
first address in a burst sequence and automatically increments
the address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Select
(BW
a,b,c,d
for 1360V25/1364V25 and BW
a,b
for 1362V25) in-
puts. A Global Write Enable (GW) overrides all byte write in-
puts and writes data to all four bytes. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to provide prop-
er data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
Functional Description
The CY7C1360V25, CY7C1364V25 and CY7C1362V25 are
2.5V, 256K x 36, 256K x 32 and 512K x 18 synchronous-pipe-
lined cache SRAM, respectively. They are designed to support
zero wait state secondary cache with minimal glue logic.
Logic Block Diagram
CLK
CE
ADV
A
x
GW
CE
1
CE
2
CE
3
BWE
BW
x
MODE
ADSP
ADSC
ZZ
OE
1360V25
A
[17:0]
DQ
a,b,c,d
DP
a,b,c,d
BW
a,b,c,d
1362V25
A
[18:0]
DQ
a,b
DP
a,b
BW
a,b
1364V25
A
[18:0]
DQ
a,b
NC
BW
a,b
CONTROL
and WRITE
LOGIC
256Kx36/
512Kx18
MEMORY
ARRAY
D
Data-In REG.
Q
CLK
OOUTPUT
REGISTERS
and LOGIC
DQ
x
DP
x
A
X
DQ
X
DP
X
BW
X
Intel and Pentium are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
• 408-943-2600
October 20, 2000
PRELIMINARY
Pin Configurations
100-Pin TQFP
CY7C1360V25
CY7C1362V25
CY7C1364V25
A
A
CE
1
CE
2
BW d
BW c
BW b
BW a
CE
3
V
DD
V
SS
C LK
GW
BWE
OE
A DS C
A DS P
A DV
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
N C ,D Q P c
DQc
DQc
V
DD Q
V
S SQ
DQc
DQc
DQc
DQc
V
S SQ
V
DD Q
DQc
DQc
V
DD
V
DD
NC
V
SS
DQd
DQd
V
DD Q
V
S SQ
DQd
DQd
DQd
DQd
V
S SQ
V
DD Q
DQd
DQd
N C ,D Q P d
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
C Y7C 1360/1364
(256K X 36/256K x 32)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N C ,D Q P b
DQb
DQb
V
DDQ
V
SS Q
DQb
DQb
DQb
DQb
V
SS Q
V
DDQ
DQb
DQb
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SS Q
DQa
DQa
DQa
DQa
V
SS Q
V
DDQ
DQa
DQa
N C ,D Q P a
NC
NC
NC
V
DD Q
V
S SQ
NC
NC
DQb
DQb
V
S SQ
V
DD Q
DQb
DQb
V
DD
V
DD
NC
V
SS
DQb
DQb
V
DD Q
V
S SQ
DQb
DQb
DPb
NC
V
S SQ
V
DD Q
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
C E
1
C E
2
NC
NC
BWb
BWa
C E
3
V
DD
V
SS
CLK
GW
BW E
OE
AD SC
AD SP
AD V
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
C Y7C 1362
(512K x 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS Q
NC
D Pa
DQa
DQa
V
SS Q
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SS Q
DQa
DQa
NC
NC
V
SS Q
V
DDQ
NC
NC
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
M O DE
A
A
A
A
A
1
A
0
D NU
D NU
V
SS
V
DD
D NU
A
A
A
A
A
A
A
A
2
MODE
A
A
A
A
A
1
A
0
DN U
DN U
V
SS
V
DD
DN U
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PRELIMINARY
Pin Configurations
(continued)
119-Ball BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
c
DQ
c
V
DDQ
DQ
c
DQ
c
V
DDQ
DQ
d
DQ
d
V
DDQ
DQ
d
DQ
d
NC
NC
V
DDQ
CY7C1360/1364 (256K x 36/256K x 32)
2
3
4
5
A
A
ADSP
A
CE
2
A
NC,DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
V
DD
DQ
d
DQ
d
DQ
d
DQ
d
NC,DQP
d
A
NC
TMS
A
A
V
SS
V
SS
V
SS
BW
c
V
SS
NC
V
SS
BW
d
V
SS
V
SS
V
SS
MODE
A
TDI
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
A
TCK
A
A
V
SS
V
SS
V
SS
BW
b
V
SS
NC
V
SS
BW
a
V
SS
V
SS
V
SS
NC
A
TDO
6
A
A
A
NC,DQP
b
DQ
b
DQ
b
DQ
b
DQ
b
V
DD
DQ
a
DQ
a
DQ
a
DQ
a
NC,DQP
a
A
NC
DNU
7
V
DDQ
NC
NC
DQ
b
DQ
b
V
DDQ
DQ
b
DQ
b
V
DDQ
DQ
a
DQ
a
V
DDQ
DQ
a
DQ
a
NC
ZZ
V
DDQ
CY7C1360V25
CY7C1362V25
CY7C1364V25
CY7C1362 (512K x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
b
NC
V
DDQ
NC
DQ
b
V
DDQ
NC
DQ
b
V
DDQ
DQ
b
NC
NC
NC
V
DDQ
2
A
CE
2
A
NC
DQ
b
NC
DQ
b
NC
V
DD
DQ
b
NC
DQ
b
NC
DQP
b
A
A
TMS
3
A
A
A
V
SS
V
SS
V
SS
BW
b
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A
TDI
4
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
Vdd
NC
TCK
5
A
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
BW
a
V
SS
V
SS
V
SS
NC
A
TDO
6
A
A
A
DQP
a
NC
DQ
a
NC
DQ
d
V
DD
NC
DQ
a
NC
DQ
a
NC
A
A
DNU
7
V
DDQ
NC
NC
NC
DQ
a
V
DDQ
DQ
a
NC
V
DDQ
DQ
a
NC
V
DDQ
NC
DQ
a
NC
ZZ
V
DDQ
3
PRELIMINARY
Selection Guide
CY7C1360V25
CY7C1362V25
CY7C1364V25
7C1360V25-200 7C1360V25-166 7C1360V25-133 7C1360V25-100
7C1364V25-200 7C1364V25-166 7C1364V25-133 7C1364V25-100
7C1362V25-200 7C1362V25-166 7C1362V25-133 7C1362V25-100
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current
(mA)
Commercial
3.1
450
10
3.5
400
10
4.0
350
10
5.0
325
10
Pin Definitions (100-Pin TQFP)
Name
A0
A1
A
BW
a
BW
b
BW
c
BW
d
GW
I/O
Input-
Synchronous
Input-
Synchronous
Description
Address Inputs used to select one of the address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and
CE
3
are sampled active. A
[1:0]
feed the 2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
Input-
Synchronous
Input-
Synchronous
Input-Clock
Global Write Enable Input, active LOW. When asserted LOW on the rising edge
of CLK, a global write is conducted (ALL bytes are written, regardless of the
values on BW
a,b,c,d
and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ignored
if CE
1
is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE
1
and CE
2
to select/deselect the device.
Output Enable, asynchronous input, active LOW. Controls the direction of the
I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH,
I/O pins are three-stated, and act as input data pins. OE is masked during the
first clock of a read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it
automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When
asserted LOW, A is captured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized. ASDP is ignored when CE
1
is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK. When
asserted LOW, A
[x:0]
is captured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized.
Selects Burst Order. When tied to GND selects linear burst sequence. When
tied to V
DDQ
or left floating selects interleaved burst sequence. This is a strap
pin and should remain static during device operation.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical
“sleep” condition with data integrity preserved.
BWE
CLK
CE
1
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CE
2
CE
3
OE
ADV
ADSP
Input-
Synchronous
Input-
Synchronous
ADSC
Input-
Synchronous
MODE
Input-
Static
Input-
Asynchronous
ZZ
4
PRELIMINARY
Pin Definitions (100-Pin TQFP)
(continued)
Name
DQ
a
DQ
b
DQ
c
DQ
d
I/O
I/O-
Synchronous
Description
CY7C1360V25
CY7C1362V25
CY7C1364V25
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A during the previous clock rise
of the read cycle. The direction of the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs. When HIGH, DQ
a
and DP
a
are
placed in a three-state condition.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A during the previous clock rise
of the read cycle. The direction of the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs. When HIGH, DQ
x
and DP
x
are
placed in a three-state condition.
These are not connect pins on the CY7C1364.
Power supply inputs to the core of the device. Should be connected to 2.5V
power supply.
Ground for the core of the device. Should be connected to ground of the sys-
tem.
Power supply for the I/O circuitry. Should be connected to a 2.5V power supply.
Ground for the I/O circuitry. Should be connected to ground of the system.
No Connects.
Do Not Use Pin. This pin is used for the expansion to the 16M density.
Do Not Use Pins. These pins should be left floating or tied to V
SS
.
NC,DQP
a
NC,DQP
b
NC,DQP
c
NC,DQP
d
I/O-
Synchronous
V
DD
V
SS
V
DDQ
V
SSQ
NC
DNU
DNU
Power Supply
Ground
I/O Power
Supply
I/O Ground
-
Pin Definitions (119-Ball BGA)
Name
A0
A1
A
BW
a
BW
b
BW
c
BW
d
GW
I/O
Input-
Synchronous
Input-
Synchronous
Description
Address Inputs used to select one of the address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
feed the 2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of CLK.
Input-
Synchronous
Input-
Synchronous
Input-Clock
Global Write Enable Input, active LOW. When asserted LOW on the rising edge
of CLK, a global write is conducted (ALL bytes are written, regardless of the
values on BW
a,b,c,d
and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst opera-
tion.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ignored
if CE
1
is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device. This pin is also
used for expansion to a 16M density SRAM.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
2
to select/deselect the device.
BWE
CLK
CE
1
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
CE
2
CE
3
5
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