3.3 VOLT CMOS SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18,
2,048 x 18, and 4,096 x 18
IDT72V205, IDT72V215,
IDT72V225, IDT72V235,
IDT72V245
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DESCRIPTION:
The IDT72V205/72V215/72V225/72V235/72V245 are functionally com-
patible versions of the IDT72205LB/72215LB/72225LB/72235LB/72245LB,
designed to run off a 3.3V supply for exceptionally low power consumption.
These devices are very high-speed, low-power First-In, First-Out (FIFO)
memories with clocked read and write controls. These FIFOs are applicable
for a wide variety of data buffering needs, such as optical disk controllers, Local
Area Networks (LANs), and interprocessor communication.
These FIFOs have 18-bit input and output ports. The input port is controlled
by a free-running clock (WCLK), and an input enable pin (WEN). Data is read
into the synchronous FIFO on every clock when
WEN
is asserted. The output
port is controlled by another clock pin (RCLK) and another enable pin (REN).
The Read Clock(RCLK) can be tied to the Write Clock for single clock operation
or the two clocks can run asynchronous of one another for dual-clock operation.
An Output Enable pin (OE) is provided on the read port for three-state control
of the output.
The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready
(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,
Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the program-
256 x 18-bit organization array (IDT72V205)
512 x 18-bit organization array (IDT72V215)
1,024 x 18-bit organization array (IDT72V225)
2,048 x 18-bit organization array (IDT72V235)
4,096 x 18-bit organization array (IDT72V245)
10 ns read/write cycle time
5V input tolerant
IDT Standard or First Word Fall Through timing
Single or double register-buffered Empty and Full flags
Easily expandable in depth and width
Asynchronous or coincident Read and Write Clocks
Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings
Half-Full flag capability
Output enable puts output data bus in high-impedanc state
High-performance submicron CMOS technology
Available in a 64-lead thin quad flatpack (TQFP/STQFP)
Industrial temperature range (–40°C to +85°C) is available
°
°
FUNCTIONAL BLOCK DIAGRAM
WEN
WCLK
D0-D17
LD
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF/(WXO)
WRITE CONTROL
LOGIC
FLAG
LOGIC
RAM ARRAY
256 x 18, 512 x 18
1,024 x 18, 2,048 x 18
4,096 x 18
WRITE POINTER
FL
WXI
(HF)/WXO
RXI
RXO
RS
READ POINTER
READ CONTROL
LOGIC
EXPANSION LOGIC
OUTPUT REGISTER
RESET LOGIC
OE
Q0-Q17
RCLK
REN
4294 drw 01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2002
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEBRUARY 2002
DSC-4294/3
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
mable flags is controlled by a simple state machine, and is initiated by asserting
the Load pin (LD). A Half-Full flag (HF) is available when the FIFO is used
in a single device configuration.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall-Through (FWFT) mode.
In IDT Standard Mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating
REN
and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A
REN
does
not have to be asserted for accessing the first word.
These devices are depth expandable using a Daisy-Chain technique or
First Word Fall Through mode (FWFT). The
XI
and
XO
pins are used to expand
the FIFOs. In depth expansion configuration, First Load (FL) is grounded on
the first device and set to HIGH for all other devices in the Daisy Chain.
The IDT72V205/72V215/72V225/72V235/72V245 are fabricated using
IDT’s high-speed submicron CMOS technology.
PIN CONFIGURATIONS
D
16
D
17
GND
RCLK
REN
LD
OE
RS
V
CC
GND
EF
Q
17
Q
16
GND
Q
15
V
CC
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
FL
WCLK
WEN
WXI
V
CC
PAF
RXI
FF
WXO/HF
RXO
Q
0
Q
1
GND
Q
2
Q
3
PAE
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
Q
6
Q
5
GND
Q
4
V
CC
4294 drw 02
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
2
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
D0–D17
RS
WCLK
WEN
RCLK
REN
OE
LD
Name
Data Inputs
Reset
Write Clock
Write Enable
Read Clock
Read Enable
Output Enable
Load
I
I
I
I
I
I
I
I
I/O
Description
Data inputs for an 18-bit bus.
When
RS
is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF
and
PAF
go HIGH, and
PAE
and
EF
go LOW. A reset is required before an initial WRITE after power-up.
When
WEN
is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.
When
WEN
is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. When
WEN
is
HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the
FF
is LOW.
When
REN
is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty.
When
REN
is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When
REN
is HIGH,
the output register holds the previous data. Data will not be read from the FIFO if the
EF
is LOW.
When
OE
is LOW, the data output bus is active. If
OE
is HIGH, the output data bus will be in a high-impedance
state.
When
LD
is LOW, data on the inputs D0–D11 is written to the offset and depth registers on the LOW-to-HIGH
transition of the WCLK, when
WEN
is LOW. When
LD
is LOW, data on the outputs Q0–Q11 is read from the
offset and depth registers on the LOW-to-HIGH transition of the RCLK, when
REN
is LOW.
In the single device or width expansion configuration,
FL
together with
WXI
and
RXI
determine if the mode is
IDT Standard mode or First Word Fall Through (FWFT) mode, as well as whether the
PAE/PAF
flags are
synchronous or asynchronous. (See Table 1.) In the Daisy Chain Depth Expansion configuration,
FL
is
grounded on the first device (first load device) and set to HIGH for all other devices in the Daisy Chain.
In the single device or width expansion configuration,
WXI
together with
FL
and
RXI
determine if the mode
is IDT Standard mode or FWFT mode, as well as whether the
PAE/PAF
flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration,
WXI
is connected to
WXO
(Write Expansion
Out) of the previous device.
In the single device or width expansion configuration,
RXI
together with
FL
and
WXI,
determine if the mode
is IDT Standard mode or FWFT mode, as well as whether the
PAE/PAF
flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration,
RXI
is connected to
RXO
(Read Expansion
Out) of the previous device.
In the IDT Standard mode, the
FF
function is selected.
FF
indicates whether or not the FIFO memory is full. In
the FWFT mode, the
IR
function is selected.
IR
indicates whether or not there is space available for writing to
the FIFO memory.
In the IDT Standard mode, the
EF
function is selected.
EF
indicates whether or not the FIFO memory is empty.
In FWFT mode, the
OR
function is selected.
OR
indicates whether or not there is valid data available at the outputs.
When
PAE
is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
offset at reset is 31 from empty for IDT72V205, 63 from empty for IDT72V215, and 127 from empty for IDT72V225/
72V235/72V245.
When
PAF
is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset at
reset is 31 from full for IDT72V205, 63 from full for IDT72V215, and 127 from full for IDT72V225/72V235/72V245.
In the single device or width expansion configuration, the device is more than half full when
HF
is LOW. In the
depth expansion configuration, a pulse is sent from
WXO
to
WXI
of the next device when the last location in the
FIFO is written.
In the depth expansion configuration, a pulse is sent from
RXO
to
RXI
of the next device when the last
location in the FIFO is read.
Data outputs for an 18-bit bus.
+3.3V power supply pins.
Seven ground pins.
FL
First Load
I
WXI
Write Expansion
Input
I
RXI
Read Expansion
Input
I
FF/IR
Full Flag/
Input Ready
Empty Flag/
Output Ready
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Write Expansion
Out/Half-Full Flag
Read Expansion
Out
Data Outputs
Power
Ground
O
EF/OR
PAE
O
O
PAF
WXO/HF
O
O
RXO
Q0–Q17
V
CC
GND
O
O
3
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
(2)
T
STG
I
OUT
Rating
Terminal Voltage
with respect to GND
Storage
Temperature
DC Output Current
Commercial
–0.5 to +5
–55 to +125
–50 to +50
Unit
V
°C
mA
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
(1)
T
A
T
A
Parameter
Supply Voltage
Commercial/Industrial
Supply Voltage
Input High Voltage
Commercial/Industrial
Input Low Voltage
Commercial/Industrial
Operating Temperature
Commercial
Operating Temperature
Industrial
Min.
3.0
0
2.0
-0.5
0
-40
Typ.
3.3
0
—
—
—
Max.
3.6
0
5.5
0.8
70
85
Unit
V
V
V
V
°C
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminal only.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 3.3V ± 0.3V, T
A
= 0
°
C to +70
°
C; Industrial: V
CC
= 3.3V
±
0.3V, TA = -40°C to +85°C)
IDT72V205
IDT72V215
IDT72V225
IDT72V235
IDT72V245
Commercial & Industrial
(1)
t
CLK
= 10, 15, 20 ns
Typ.
—
—
—
—
—
—
Symbol
I
LI
(2)
I
LO
(3)
V
OH
V
OL
I
CC1
(4,5,6)
I
CC2
(4.7)
Parameter
Input Leakage Current (any input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2 mA
Output Logic “0” Voltage, I
OL
= 8 mA
Active Power Supply Current
Standby Current
Min.
–1
–10
2.4
—
—
—
Max.
1
10
—
0.4
30
5
Unit
µA
µA
V
V
mA
mA
NOTES:
1. Industrial Temperature Range Product for the 15ns speed grade is available as a standard device.
2. Measurements with 0.4
≤
V
IN
≤
V
CC
.
3.
OE
≥
V
IH,
0.4
≤
V
OUT
≤
V
CC
.
4. Tested with outputs disabled (I
OUT
= 0).
5. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz.
6. Typical I
CC1
= 2.04 + 0.88*f
S
+ 0.02*C
L
*f
S
(in mA).
These equations are valid under the following conditions:
V
CC
= 3.3V, T
A
= 25
°
C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f
S
/2, C
L
= capacitive load (in pF).
7. All Inputs = V
CC
- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE
(T
A
= +25
°
C, f = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
Parameter
(1)
Input
Capacitance
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
NOTES:
1. With output deselected, (OE
≥
V
IH
).
2. Characterized values, not currently tested.
4
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
Commercial
IDT72V205L10
IDT72V215L10
IDT72V225L10
IDT72V235L10
IDT72V245L10
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAFA
t
PAFS
t
PAEA
t
PAES
t
HF
t
XO
t
XI
t
XIS
t
SKEW1
t
SKEW2(4)
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-up Time
Data Hold Time
Enable Set-up Time
Enable Hold Time
Reset Pulse Width
(2)
Reset Set-up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z
(3)
Output Enable to Output Valid
Output Enable to Output in High-Z
(3)
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Asynchronous Programmable Almost-Full Flag
Write Clock to Synchronous ProgrammableAlmost-Full Flag
Clock to Asynchronous Programmable Almost-Empty Flag
Read Clock to Synchronous Programmable Almost-Empty Flag
Clock to Half-Full Flag
Clock to Expansion Out
Expansion In Pulse Width
Expansion In Set-Up Time
Skew time between Read Clock & Write Clock for
FF/IR
and
EF/OR
Skew time between Read Clock & Write Clock for
PAE
and
PAF
Min.
—
2
10
4.5
4.5
3
0.5
3
0.5
10
8
8
—
0
—
1
—
—
—
—
—
—
—
—
3
3
5
14
Max.
100
6.5
—
—
—
—
—
—
—
—
—
—
15
—
6
6
6.5
6.5
17
8
17
8
17
6.5
—
—
—
—
Com'l & Ind'l
(1)
IDT72V205L15
IDT72V215L15
IDT72V225L15
IDT72V235L15
IDT72V245L15
Min.
—
2
15
6
6
4
1
4
1
15
10
10
—
0
3
3
—
—
—
—
—
—
—
—
6.5
5
6
18
Max.
66.7
10
—
—
—
—
—
—
—
—
—
—
15
—
8
8
10
10
20
10
20
10
20
10
—
—
—
—
Commercial
IDT72V205L20
IDT72V215L20
IDT72V225L20
IDT72V235L20
IDT72V245L20
Min.
—
2
20
8
8
5
1
5
1
20
12
12
—
0
3
3
—
—
—
—
—
—
—
—
8
8
8
20
Max.
50
12
—
—
—
—
—
—
—
—
—
—
20
—
10
10
12
12
22
12
22
12
22
12
—
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. t
SKEW2
applies to synchronous
PAE
and synchronous
PAF
only.
3.3V
330Ω
D.U.T.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
5
510Ω
30pF*
4294 drw 03
Figure 1. Output Load
* Includes jig and scope capacitances.
FPGA/CPLD
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