73S8024RN
Low Cost Smart Card Interface
DATA SHEET
August 2005
DESCRIPTION
The TERIDIAN 73S8024RN is a single smart card (ICC)
interface IC that can be controlled by a dedicated control bus.
The TERIDIAN 73S8024RN has been designed to provide
full electrical compliance with ISO-7816-3, EMV 4.0
(EMV2000) and NDS specifications.
Interfacing with the system controller is done through a
control bus, composed of digital inputs to control the
interface, and one interrupt output to inform the system
controller of the card presence and faults.
The card clock can be generated by an on-chip oscillator
using an external crystal or by connection to a clock signal.
TERIDIAN 73S8024RN incorporates an ISO-7816-3
activation/deactivation sequencer that controls the card
signals. Level-shifters drive the card signals with the selected
card voltage (3V or 5V), coming from an internal Low Drop-
Out (LDO) voltage regulator. This LDO regulator is powered
by a dedicated power supply input V
PC
. Digital circuitry is
separately powered by a digital power supply V
DD
.
With its embedded LDO regulator, the TERIDIAN
73S8024RN is a cost-effective solution for any application
where a 5V (typically -5% +10%) power supply is available.
Hardware support for auxiliary I/O lines, C4 / C8 contacts, is
provided*.
Emergency card deactivation is initiated upon card extraction
or upon any fault generated by the protection circuitry. The
fault can be a card over-current, a V
DD
(digital power
supply)**, a V
PC
(regulator power supply), a V
CC
(card power
supply) or an over-heating fault.
The card over-current circuitry is a true current detection
function, as opposed to V
CC
voltage drop detection, as usually
implemented in ICC interface ICs.
The V
DD
voltage fault has a threshold voltage that can be
adjusted with an external resistor or resistor network. It allows
automated card deactivation at a customized V
DD
voltage
threshold value. It can be used, for instance, to match the
system controller operating voltage range.
ADVANTAGES
•
Traditional step-up converter is replaced by a LDO
regulator:
Greatly reduced power dissipation
Fewer external components are required
Better noise performance
High current capability (90mA supplied to the card)
•
•
•
•
SO28 package is Pin-to-pin compatible with industry-
standard TDA8004 and TDA8024
Card clock STOP (high and low) mode
Small format (4x4x0.85mm) 20QFN package option
True card over-current detection
FEATURES
•
Card Interface:
Complies with ISO-7816-3, EMV 4.0 and NDS
A LDO voltage regulator provides 3V / 5V to the card
from an external power supply input
Provides at least 90mA to the card
ISO-7816-3 Activation / Deactivation sequencer with
emergency automated deactivation on card removal
or fault detected by the protection circuitry
Protection includes 3 voltage supervisors that detect
voltage drops on V
CC
(card), V
DD
(digital)**, and V
PC
(regulator) power supplies
The V
DD
voltage supervisor threshold value can be
externally adjusted**
Over-current detection 150mA max.
Card clock stop high or low*
2 card detection inputs, 1 for each possible user polarity
Auxiliary I/O lines, for C4 / C8 contact signals*
Card CLK clock frequency up to 20MHz
System Controller Interface:
3 Digital inputs control the card activation /
deactivation, card reset and card voltage
4 Digital inputs control the card clock (division rate and
card clock stop modes)
1 Digital output, interrupt to the system controller,
allows the system controller to monitor the card
presence and faults.
Crystal oscillator or host clock, up to 27MHz
Regulator Power Supply:
4.75V to 5.5V (EMV 4.0)
4.85V to 5.5V (NDS)
Digital Interfacing: 2.7V to 5.5V
6kV ESD Protection on the card interface
Package: SO28, 20QFN or 32QFN
Rev 1.5
•
APPLICATIONS
•
•
•
Set-Top-Box Conditional Access and Pay-per-View
Point of Sales & Transaction Terminals
Control Access & Identification
•
* Pins/functions not available on 20 pin QFN package.
** User V
DD_FLT
threshold configuration not available on 20 QFN package.
•
•
•
Page: 1 of 23
©
2005 TERIDIAN Semiconductor Corporation
73S8024RN
Low Cost Smart Card Interface
DATA SHEET
FUNCTIONAL DIAGRAM
VDD
21 [20] {12}
VDDF_ADJ
18 [17]
NC
5 [9,16,25,32]
VPC
6
6 [3] {2}
V
PC
FAULT
{13} [21] 22
GND
DIGITAL POWER SUPPLY
VDD VOLTAGE SUPERVISOR
VOLTAGE REFERENCE
V
DD
FAULT
V
CC
FAULT
I
CC
FAULT
{10} [18] 19
CMDVCC
{11} [19] 20
RSTIN
{20} [31] 3
5V/3V
{14} [22] 23
OFF
{18} [29] 1
CLKDIV1
{19} [30] 2
CLKDIV2
{15} [23] 24
XTALIN
{16} [24] 25
XTALOUT
[4] 7
CLKSTOP
[5] 8
CLKLEV
Int_Clk
LDO
REGULATOR
&
VOLTAGE
SUPERVISORS
4 [1] {1}
GND
14 [12] {6}
GND
17 [15] {9}
VCC
DIGITAL
CIRCUITRY
&
FAULT LOGIC
R-C
OSC.
ICC RESET
BUFFER
16 [14] {8}
RST
ISO-7816
SEQUENCER
XTAL
OSC
CLOCK
GENERATION
ICC CLOCK
BUFFER
15 [13] {7}
CLK
10 [7] {4}
PRES
9 [6] {3}
PRES
OVER
TEMP
TEMP FAULT
{17} [26] 26
I/OUC
[27] 27
AUX1UC
[28] 28
AUX2UC
11 [8] {5}
I/O
ICC I/O BUFFERS
13 [11]
AUX1
12 [10]
AUX2
Pin numbers reference to the SO28 package
[Pin numbers] reference to the QFN32 package
{Pin numbers} reference to the QFN20 package
Figure 1: 73S8024RN Block Diagram
Page: 2 of 23
©
2005 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8024RN
Low Cost Smart Card Interface
DATA SHEET
PIN DESCRIPTION
CARD INTERFACE
NAME
I/O
AUX1
AUX2
RST
CLK
PIN
28SO
11
13
12
16
15
PIN
20QFN
5
---
---
8
7
PIN
32QFN
8
11
10
14
13
DESCRIPTION
Card I/O: Data signal to/from card. Includes a pull-up resistor to V
CC.
AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to V
CC.
AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to V
CC.
Card reset: provides reset (RST) signal to card.
Card clock: provides clock signal (CLK) to card. The rate of this clock is determined by
the external crystal frequency or frequency of the external clock signal applied on
XTALIN and CLKDIV selections.
Card Presence switch: active high indicates card is present. Should be tied to GND
when not used, but it Includes a high-impedance pull-down current source.
Card Presence switch: active low indicates card is present. Should be tied to V
DD
when
not used, but it Includes a high-impedance pull-up current source.
Card power supply – logically controlled by sequencer, output of LDO regulator.
Requires an external filter capacitor to the card GND
Card ground
PRES
PRES
VCC
GND
10
9
17
14
4
3
9
6
7
6
15
12
MISCELLANEOUS INPUTS AND OUTPUTS
NAME
XTALIN
XTALOUT
VDDF_ADJ
NC
PIN
28SO
24
25
18
5
PIN
20QFN
15
16
---
---
PIN
DESCRIPTION
32QFN
23
24
17
9, 16,
25, 32
Crystal oscillator input: can either be connected to crystal or driven as a source for
the card clock.
Crystal oscillator output: connected to crystal. Left open if XTALIN is being used as
external clock input.
V
DD
fault threshold adjustment input: this pin can be used to adjust the V
DDF
values
(that controls deactivation of the card). Must be left open if unused.
Non-connected pin.
POWER SUPPLY AND GROUND
NAME
VDD
VPC
GND
GND
PIN
28SO
21
6
4
22
PIN
20QFN
12
2
1
13
PIN
DESCRIPTION
32QFN
20
3
1
21
System interface supply voltage and supply voltage for internal circuitry.
LDO regulator power supply source.
LDO Regulator ground.
Digital ground.
Page: 3 of 23
©
2005 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8024RN
Low Cost Smart Card Interface
DATA SHEET
MICROCONTROLLER INTERFACE
NAME
CMDVCC
PIN
28SO
19
PIN
20QFN
10
PIN
32QFN
18
DESCRIPTION
Command VCC (negative assertion): Logic low on this pin causes the LDO regulator to ramp
the V
CC
supply to the card and initiates a card activation sequence, if a card is present.
5 volt / 3 volt card selection: Logic one selects 5 volts for V
CC
and card interface, logic low
selects 3 volt operation. When the part is to be used with a single card voltage, this pin should
be tied to either GND or V
DD
. However, it includes a high impedance pull-up resistor to default
this pin high (selection of 5V card) when not connected.
Stops the card clock signal during a card session when set high (card clock STOP mode).
Internal pull-down resistor allows this pin to be left as an open circuit if the clock STOP mode
is not used.
Sets the logic level of the card clock STOP mode when the clock is de-activated by setting pin
7 high. Logic low selects card STOP low. Logic high selects card STOP high. Internal pull-
down resistor allows this pin to be left as an open circuit if the clock STOP mode is not used.
Sets the divide ratio from the XTAL oscillator (or external clock input) to the card clock. These
pins include pull-down resistors.
CLKDIV1
0
0
1
1
OFF
RSTIN
I/OUC
AUX1UC
AUX2UC
23
20
26
27
28
14
11
17
---
---
22
19
26
27
28
CLKDIV2
0
1
1
0
CLOCK RATE
XTALIN/8
XTALIN/4
XTALIN/2
XTALIN
5V/#V
3
20
31
CLKSTOP
7
---
4
CLKLVL
8
1
2
---
5
29
30
CLKDIV1
CLKDIV2
18
19
Interrupt signal to the processor. Active Low - Multi-function indicating fault conditions and
card presence. Open drain output configuration – It includes an internal 22kΩ pull-up to V
DD.
Reset Input: This signal is the reset command to the card.
System controller data I/O to/from the card. Includes a pull-up resistor to V
DD.
System controller auxiliary data I/O to/from the card. Includes a pull-up resistor to V
DD.
System controller auxiliary data I/O to/from the card. Includes a pull-up resistor to V
DD.
SYSTEM CONTROLLER INTERFACE
3 separated digital inputs allow direct control of the card interface from the host as follows:
Pin
CMDVCC:
When low, starts an activation sequence
Pin RSTIN: controls the card Reset signal (when enabled by the sequencer)
Pin 5V/#V: Defines the card voltage
Card clock is controlled by 4 digital inputs:
CLKDIV1 and CLKDIV2 define the division rate for the clock frequency, from the input
clock frequency (crystal or external clock)
CLKSTOP (active high) allows card power down mode by stopping the card clock
CLKLEV defines the card clock level of the card power down mode.
Interrupt output to the host: As long as the card is not activated, the
OFF
pin informs the host about the card
presence only (Low = No card in the reader). When
CMDVCC
is set low (Card activation sequence requested
from the host), low level on
OFF
means a fault has been detected (e.g. card removal during card session, or
voltage fault, or thermal / over-current fault) that automatically initiates a deactivation sequence.
Page: 4 of 23
©
2005 TERIDIAN Semiconductor Corporation
Rev 1.5
73S8024RN
Low Cost Smart Card Interface
DATA SHEET
POWER SUPPLY AND VOLTAGE SUPERVISON
The TERIDIAN 73S8024RN smart card interface IC incorporates a LDO voltage regulator. The voltage output is
controlled by the digital input 5V/#V. This regulator is able to provide either 3V or 5V card voltage from the power
supply applied on the VPC pin.
Digital circuitry is powered by the power supply applied on the VDD pin. V
DD
also defines the voltage range to
interface with the system controller.
Three voltage supervisors constantly check the presence of the voltages V
DD
, V
PC
and V
CC
. A card deactivation
sequence is forced upon fault of any of these voltage supervisors. The two voltage supervisors for V
PC
and V
CC
are linked so that a fault is generated to activate a deactivation sequence when the voltage V
PC
becomes lower
than V
CC
. It allows the 73S8024RN to operate at lower V
PC
voltage when using 3V cards only. The voltage
regulator can provide a current of at least 90mA on V
CC
that comply easily with EMV 4.0 and NDS specifications.
The V
PC
voltage supervisor threshold values are defined from applicable standards (EMV and NDS). A third
voltage supervisor monitors the V
DD
voltage. It is used to initialize the ISO-7816-3 sequencer at power-on, and to
deactivate the card at power-off or upon fault. The voltage threshold of the V
DD
voltage supervisor is internally set
by default to 2.3V nominal. However, it may be desirable, in some applications, to modify this threshold value.
The pin VDDF_ADJ (pin 18 in the SO package, pin 17 in the 32QFN package, not supported in the 20QFN
package) is used to connect an external resistor R
EXT
to ground to raise the V
DD
fault voltage to another value
V
DDF
. The resistor value is defined as follows:
R
EXT
= 56kΩ /(V
DDF
- 2.33)
An alternative method (more accurate) of adjusting the V
DD
fault voltage is to use a resistive network of R3 from
the pin to supply and R1 from the pin to ground (see applications diagram). In order to set the new threshold
voltage, the equivalent resistance must be determined. This resistance value will be designated Kx. Kx is
defined as R1/(R1+R3). Kx is calculated as:
Kx = (2.789 / V
TH
) - 0.6125 where V
TH
is the desired new threshold voltage.
To determine the values of R1 and R3, use the following formulas.
R3 = 24000 / Kx
R1 = R3*(Kx / (1 – Kx))
Taking the example above, where a V
DD
fault threshold voltage of 2.7V is desired, solving for Kx gives:
Kx = (2.789 / 2.7) - 0.6125 = 0.42046.
Solving for R3 gives:
R3 = 24000 / 0.42046 = 57080.
Solving for R1 gives:
R1 = 57080 *(0.42046 / (1 – 0.42046)) = 41412.
Using standard 1 % resistor values gives R3 = 57.6KΩ and R1 = 42.4KΩ.
These values give an equivalent resistance of Kx = 0.4228, a 0.6% error.
If the 2.3V default threshold is used, this pin must be left unconnected. The 20 QFN package has the V
DD
fault
threshold fixed at this default value.
Page: 5 of 23
©
2005 TERIDIAN Semiconductor Corporation
Rev 1.5
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
