IDTQS74FCT2821AT/BT/CT
HIGH-SPEED CMOS BUS INTERFACE 10-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
HIGH-SPEED CMOS
BUS INTERFACE
10-BIT REGISTER
FEATURES:
•
•
•
•
•
•
IDTQS74FCT2821AT/BT/CT
DESCRIPTION:
CMOS power levels: <7.5mW static
Undershoot clamp diodes on all outputs
True TTL input and output compatibility
Ground bounce controlled outputs
Reduced output swing of 0 to 3.5V
Built-in 25Ω series resistor outputs reduce reflection and other
Ω
system noise
• A, B, and C speed grades
• I
OL
= 12mA
• Available in SOIC and QSOP packages
The IDTQS74FCT2821T is a 10-bit high-speed CMOS TTL-compatible
buffered register with 3-state outputs, with a 25Ω resister that is useful for
driving transmission lines and reducing system noise. The 2821 series parts
can replace the 821 series to reduce noise in an existing design. All inputs
have clamp diodes for undershoot noise suppression. All outputs have
ground bounce suppression. Outputs will not load an active bus when Vcc
is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
OE
D
Dx
CP
CP
Q
25Ω
Yx
INDUSTRIAL TEMPERATURE RANGE
1
c
2002 Integrated Device Technology, Inc.
MARCH 2002
DSC-5256/4
IDTQS74FCT2821AT/BT/CT
HIGH-SPEED CMOS BUS INTERFACE 10-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
CP
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
I
OUT
I
IK
I
OK
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current Max Sink Current/Pin
Input Diode Current, V
IN
< 0
Output Diode Current, V
OUT
< 0
Max
–0.5 to +7
–65 to +150
120
–20
–50
Unit
V
°C
mA
mA
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
IN
(2)
(3)
(4)
Parameter
(1)
Input Capacitance
Input Capacitance
Output Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
IN
= 0V
V
OUT
= 0V
V
OUT
= 0V
Typ.
4
8
6
8
Max.
—
—
—
—
Unit
pF
pF
pF
pF
C
OUT
SOIC/ QSOP
TOP VIEW
C
OUT
(5)
PIN DESCRIPTION
Pin Names
Dx
CP
Yx
OE
I/O
I
I
O
I
Description
D Flip-Flop Data Inputs
Clock Pulse for the register. Enters data into the register
on the LOW-to-HIGH transition.
Register 3-State Outputs
Output Control. When the
OE
input is HIGH, the Yx
outputs are in the high impedance state. When the
OE
input is LOW, the TRUE register data is present at the
Yx outputs.
NOTES:
1. This parameter is measured at characterization but not tested.
2. Pins 1, 3-11, 13.
3. Pin 2.
4. Pins 15-22.
5. Pins 14, 23.
FUNCTION TABLE
(1)
Inputs
OE
H
H
H
H
L
L
Dx
L
H
L
H
L
H
CP
↑
↑
↑
↑
↑
↑
Internal
Value Qx
L
H
L
H
L
H
Outputs
Yx
Z
Z
Z
Z
L
H
Function
High-Z
High-Z
Load
Load
Load
Load
LOGIC SYMBOL
Dx
10
D
CP
Q
10
Yx
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
Z = High-Impedance
↑
= LOW-to-HIGH transition
CP
OE
2
IDTQS74FCT2821AT/BT/CT
HIGH-SPEED CMOS BUS INTERFACE 10-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±5%
Symbol
V
IH
V
IL
∆V
T
I
IH
I
IL
I
OZ
I
OR
V
IC
V
OH
V
OL
R
OUT
(3)
Parameter
Input HIGH Level
Input LOW Level
Input Hysteresis
Input HIGH Current
Input LOW Current
Off-State Output Current (Hi-Z)
Current Drive
Input Clamp Voltage
Output HIGH Voltage
Output LOW Voltage
Output Resistance
V
CC
= Max
0
≤
V
IN
≤
V
CC
—
50
—
2.4
—
18
—
—
–0.7
—
—
25
±5
—
–1.2
—
0.5
40
µA
mA
V
V
V
Ω
V
CC
= Max., V
OUT
= 2.0V
(2)
V
CC
= Min, I
IN
= -18mA , T
A
= 25°C
(2)
V
CC
= Min.
V
CC
= Min.
V
CC
= Min.
I
OH
= -15mA
I
OL
= 12mA
I
OH
= 12mA
Test Conditions
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
TLH
- V
THL
for all inputs
V
CC
= Max.
0
≤
V
IN
≤
V
CC
Min.
2
—
—
—
Typ.
(1)
—
—
0.2
—
Max.
—
0.8
—
±5
Unit
V
V
V
µA
NOTES:
1. Typical values are at V
CC
= 5.0V, T
A
= 25°C.
2. This parameter is measured at characterization but not tested.
3. R
OUT
changed on March 8, 2002. See rear page for more information.
POWER SUPPLY CHARACTERISTICS
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 5%
Symbol
I
CC
Parameter
Quiescent Power Supply Current
∆I
CC
Supply Current per Input TTL Inputs HIGH
I
CCD
Supply Current per Input per MHz
Test Conditions
(1)
V
CC
= Max.
freq = 0
0V
≤
V
IN
≤
0.2V or
V
CC
- 0.2V
≤
V
IN
≤
Vcc
V
CC
= Max.
V
IN
= 3.4V
(2)
freq = 0
V
CC
= Max.
Outputs Open and Enabled
One Bit Toggling
50% Duty Cycle
Other inputs at GND or Vcc
(3,4)
Min.
—
Max.
1.5
Unit
mA
—
2
mA
—
0.25
mA/MHz
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Per TLL driven input (V
IN
= 3.4V).
3. For flip-flops, I
CCD
is measured by switching one of the data input pins so that the output changes every clock cycle. This is a measurement of device power consumption
only and does not include power to drive load capacitance or tester capacitance.
4. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
3
IDTQS74FCT2821AT/BT/CT
HIGH-SPEED CMOS BUS INTERFACE 10-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(1)
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
S
t
H
Parameter
Clock to Y Delay
OE
= LOW
Clock to Y Delay
OE
= LOW
(2)
Data to CP Setup Time
Data to CP Hold Time
FCT2821AT
Min.
Max.
—
10
—
4
2
20
—
—
FCT2821BT
Min.
Max.
—
7.5
—
3
1.5
15
—
—
FCT2821CT
Min.
Max.
—
6
—
3
1.5
12.5
—
—
Unit
ns
ns
ns
ns
NOTES:
1. C
LOAD
= 50pF, R
LOAD
= 500Ω unless otherwise noted.
2. C
LOAD
= 300pF.
TIMING REQUIREMENTS OVER OPERATING RANGE
(1)
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PHZ
t
PLZ
Parameter
(2)
Clock to Y Delay
HIGH or LOW
Output Enable Time
OE
to Yx
Output Enable Time
(3)
OE
to Yx
Output Disable Time
(4)
OE
to Yx
Output Disable Time
OE
to Yx
FCT2821AT
Min.
Max.
7
—
—
—
—
—
12
23
7
9
FCT2821BT
Min.
Max.
6
—
—
—
—
—
8
—
6.5
7.5
FCT2821CT
Min.
Max.
6
—
—
—
—
—
7
—
6.2
6.5
Unit
ns
ns
ns
ns
ns
NOTES:
1. C
LOAD
= 50pF, R
LOAD
= 500Ω unless otherwise noted.
2. See Test Circuits and Waveforms
3. C
LOAD
= 300pF.
4. C
LOAD
= 5pF.
4
IDTQS74FCT2821AT/BT/CT
HIGH-SPEED CMOS BUS INTERFACE 10-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V
CC
500Ω
Pulse
Generator
V
IN
D.U.T.
50pF
R
T
C
L
500Ω
V
OUT
7.0V
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
All Other Tests
Switch
Closed
Open
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
FCTL link
Test Circuits for All Outputs
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t
SU
t
H
t
REM
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
FCTL link
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
FCTL link
1.5V
1.5V
t
SU
t
H
Pulse Width
Set-Up, Hold, and Release Times
ENABLE
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
FCTL link
DISABLE
3V
1.5V
CONTROL
INPUT
t
PZL
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
3.5V
1.5V
t
PHZ
0.3V
1.5V
0V
t
PLZ
0V
3.5V
0.3V
V
OL
V
OH
0V
FCTL link
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
