• Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
• Operating frequency: 60MHz to 200MHz
• Standard speed: PC1600 (DDR200), PC2100 (DDR266)
• A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333)
• 1 to 10 differential clock distribution
• Very low skew (<100ps)
• Very low jitter (<75ps)
• 2.5V AV
DD
and 2.5V V
DDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 48-pin TSSOP and 56-pin VFBGA packages
The CSPT857 is a PLL based clock driver that acts as a zero delay buffer
to distribute one differential clock input pair(CLK,
CLK
) to 10 differential output
pairs (Y
[0:9]
, Y
[0:9]
) and one differential pair of feedback clock output (FBOUT,
FBOUT).
External feedback pins (FBIN,
FBIN)
for synchronization of the
outputs to the input reference is provided. A CMOS Enable/Disable pin is
available for low power disable. When the output frequency falls below
approximately 20MHz, the device will enter power down mode. In this mode,
the receivers are disabled, the PLL is turned off, and the output clock drivers
are tristated, resulting in a current consumption device of less than 200µA.
The CSPT857 requires no external components and has been optimised
for very low I/O phase error, skew, and jitter, while maintaining frequency and
duty cycle over the operating voltage and temperature range. The CSPT857,
designed for use in both module assemblies and system motherboard based
solutions, provides an optimum high-performance clock source.
The CSPT857 is only available in Industrial Temperature Range (-40°C to
+85°C), and CSPT857A is only available in Commercial Temperature Range
(0°C to +70°C). See Ordering Information for details.
FUNCTIONAL BLOCK DIAGRAM
PWRDWN
37/E6
AV
DD
16/G2
TEST
MODE
LOGIC
3/A1
Y0
2/A2
Y0
5/B2
6/B1
10/D1
9/D2
Y1
Y1
Y2
Y2
20/J2
Y3
19/J1
22/K1
Y3
Y4
23/K2
Y4
Y5
CLK
CLK
FBIN
FBIN
13/F1
14/F2
46/A6
47/A5
44/B5
43/B6
39/D6
40/D5
29/J5
30/J6
PLL
36/F6
35/F5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
27/K6
26/K5
32/H6
33/H5
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2002
Integrated Device Technology, Inc.
OCTOBER 2002
DSC-5172/8
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
PWR
DWN
6
Y
5
Y
5
Y
6
Y
6
GND
GND
NC
NC
GND
GND
C
Y
7
Y
7
NC
NC
Y
2
Y
2
D
FBIN
V
DDQ
FBOUT
Y
8
Y
8
Y
9
Y
9
5
V
DDQ
FBIN FBOUT GND
NC
NC
V
DDQ
V
DDQ
E
4
GND V
DDQ
GND V
DDQ
Y
0
Y
0
A
NC
NC
V
DDQ
GND
V
DDQ
GND
Y
3
Y
3
J
3
2
Y
1
Y
1
B
CLK
CLK
F
AV
DD
GND
V
DDQ
AGND
G
H
Y
4
Y
4
K
1
VFBGA
TOP VIEW
56 BALL VFBGA PACKAGE LAYOUT
0.65mm
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
TOP VIEW
A
1
2
3
4
5
6
B
C
D
E
F
G
H
J
K
2
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
GND
Y
0
Y
0
V
DDQ
Y
1
Y
1
GND
GND
Y
2
Y
2
V
DDQ
V
DDQ
CLK
CLK
V
DDQ
AV
DD
AGND
GND
Y
3
Y
3
V
DDQ
Y
4
Y
4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
Y
5
Y
5
V
DDQ
Y
6
Y
6
GND
GND
Y
7
Y
7
V
DDQ
PWRDWN
FBIN
FBIN
V
DDQ
FBOUT
FBOUT
GND
Y
8
Y
8
V
DDQ
Y
9
Y
9
GND
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DDQ
, AV
DD
Rating
Supply Voltage Range
Input Voltage Range
Voltage range applied to any
output in the high or low state
Input Clamp Current
Output Clamp Current
Max
–0.5 to +3.6
–0.5 to V
DDQ
+ 0.5
–0.5 to V
DDQ
+ 0.5
–50
±50
Unit
V
V
V
mA
mA
V
I(2)
V
O(2)
I
IK
(V
I
<0)
I
OK
(V
O
<0 or
V
O
> V
DDQ
)
Continuous Output Current
I
O
(V
O
=0 to V
DDQ
)
V
DDQ
or GND
TSTG
Continuous Current
Storage Temperature Range
±50
±100
– 65 to +150
mA
mA
°C
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150
°
C and a board trace length of 750 mils.
CAPACITANCE
(1)
Parameter
C
IN
C
I(∆)
C
L
Description
Input Capacitance
V
I
= V
DDQ
or GND
Delta Input Capacitance
V
I
= V
DDQ
or GND
Load Capacitance
—
14
—
pF
NOTE:
1. Unused inputs must be held high or low to prevent them from floating.
Min.
2.5
-0.25
Typ.
—
—
Max.
3.5
0.25
Unit
pF
pF
TSSOP
TOP VIEW
RECOMMENDED OPERATING CONDITIONS
CSPT857
Symbol
AV
DD
V
DDQ
T
A
Supply Voltage
I/O Supply Voltage
Operating Free-Air Temperature
Parameter
Min.
2.3
-40
Typ.
V
DDQ
2.5
Max.
2.7
+85
Min.
V
DDQ
– 0.12
2.3
0
CSPT857A
Typ.
V
DDQ
2.5
Max.
2.7
2.7
+70
Unit
V
V
°
C
3
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (TSSOP)
Pin Name
AGND
AV
DD
CLK,
CLK
FBIN,
FBIN
FBOUT,
FBOUT
GND
PWRDWN
V
DDQ
Y
[0:9]
Y
[0:9]
Pin Number
17
16
13, 14
35, 36
32, 33
1, 7, 8, 18, 24, 25, 31, 41, 42, 48
37
4, 11, 12, 15, 21, 28, 34, 38, 45
3, 5, 10, 20, 22, 27, 29, 39, 44, 46
2, 6, 9, 19, 23, 26, 30, 40, 43, 47
2.5V analog supply
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
Output enable for Y and
Y
2.5V supply
Buffered output of input clock, CLK
Buffered output of input clock,
CLK
Description
Ground for 2.5V analog supply
PIN DESCRIPTION (VFBGA)
Pin Name
AGND
AV
DD
CLK,
CLK
FBIN,
FBIN
FBOUT,
FBOUT
GND
PWRDWN
V
DDQ
Y
[0:9]
Y
[0:9]
Pin Number
H1
G2
F1, F2
F5, F6
H6, G5
A3, A4, C1, C2, C5, C6, H2, H5, K3, K4
E6
B3, B4, E1, E2, E5, G1, G6, J3, J4
A1, A6, B2, B5, D1, D6, J2, J5, K1, K6
A2, A5, B1, B6, D2, D5, J1, J6, K2, K5
2.5V analog supply
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
Output enable for Y and
Y
2.5V supply
Buffered output of input clock, CLK
Buffered output of input clock,
CLK
Description
Ground for 2.5V analog supply
FUNCTION TABLE
(1)
INPUTS
AV
DD
GND
GND
X
X
2.5V (nom)
2.5V (nom)
2.5V (nom)
(2)
PWRDWN
H
H
L
L
H
H
X
CLK
L
H
L
H
L
H
<20MHz
CLK
H
L
H
L
H
L
<20MHz
Y
L
H
Z
Z
L
H
Z
Y
H
L
Z
Z
H
L
Z
OUTPUTS
FBOUT
L
H
Z
Z
L
H
Z
FBOUT
H
L
Z
Z
H
L
Z
PLL
Bypassed/OFF
Bypassed/OFF
OFF
OFF
ON
ON
OFF
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
Z = High-Impedance OFF-State
X = Don't Care
2. Additional feature that senses when the clock input is less than approximately 20MHz and places the part in sleep mode. Reciever inputs and PLL are turned off and outputs
= tristate.
4
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C; Industrial: T
A
= –40°C to +85°C
Symbol
V
IK
V
IL (dc)
V
IH (dc)
V
IL (ac)
V
IH (ac)
V
OL
V
OH
V
IX
V
ID(DC) (1)
V
ID(AC) (1)
I
IN
I
DDPD
I
DDQ
I
ADD
Parameter
Input Clamp Voltage (All Inputs)
Static Input LOW Voltage
Static Input HIGH Voltage
Dynamic Input LOW Voltage
Dynamic Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Input Differential Cross Voltage
DC Input Differential Voltage
AC Input Differential Voltage
Input Current
Power-Down Current on V
DDQ
and A
VDD
Dynamic Power Supply Current on V
DDQ
Dynamic Power Supply Current on A
VDD
V
DDQ
= 2.7V, V
I
= 0V to 2.7V
A
VDD
/V
DDQ
= Max., CLK = 0MHz or
PWRDWN
= L
A
VDD
/V
DDQ
= Max., CLK = 200MHz, 120Ω/14pF
A
VDD
/V
DDQ
= Max., CLK = 170MHz, 120Ω/14pF
A
VDD
/V
DDQ
= Max., CLK = 170MHz
NOTE:
1. V
ID
is the magnitude of the difference between the input level on CLK and the input level on
FPGA/CPLD
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