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IDT82V2082PF: 产品描述DUAL CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT; 文件大小861KB，共79页; 制造商IDT(艾迪悌); 官网地址http://www.idt.com/

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IDT82V2082PF概述

DUAL CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT

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DUAL CHANNEL T1/E1/J1 LONG HAUL/

SHORT HAUL LINE INTERFACE UNIT

IDT82V2082

FEATURES:

•

Dual channel T1/E1/J1 long haul/short haul line interfaces

Supports HPS (Hitless Protection Switching) for 1+1 protection

without external relays

Receiver sensitivity exceeds -36 dB@772KHz and -43

dB@1024 KHz

Programmable T1/E1/J1 switchability allowing one bill of ma-

terial for any line condition

Single 3.3 V power supply with 5 V tolerance on digital inter-

faces

Meets or exceeds specifications in

- ANSI T1.102, T1.403 and T1.408

- ITU I.431, G.703, G.736, G.775 and G.823

- ETSI 300-166, 300-233 and TBR12/13

- AT&T Pub 62411

Software programmable or hardware selectable on:

- Wave-shaping templates for short haul and long haul LBO (Line

Build Out)

- Line terminating impedance (T1:100

Ω,

J1:110

Ω,

E1:75

Ω/120

Ω)

- Adjustment of arbitrary pulse shape

- JA (Jitter Attenuator) position (receive path or transmit path)

- Single rail/dual rail system interfaces

- B8ZS/HDB3/AMI line encoding/decoding

Active edge of transmit clock (TCLK) and receive clock (RCLK)

Active level of transmit data (TDATA) and receive data (RDATA)

Receiver or transmitter power down

High impedance setting for line drivers

PRBS (Pseudo Random Bit Sequence) generation and detection

with 2

-1 PRBS polynomials for E1

- QRSS (Quasi Random Sequence Signals) generation and detec-

tion with 2

-1 QRSS polynomials for T1/J1

- 16-bit BPV (Bipolar Pulse Violation) /Excess Zero/PRBS or QRSS

error counter

- Analog loopback, Digital loopback, Remote loopback and Inband

loopback

Cable attenuation indication

Adaptive receive sensitivity

Non-intrusive monitoring per ITU G.772 specification

Short circuit protection and internal protection diode for line

drivers

LOS (Loss Of Signal) & AIS (Alarm Indication Signal) detection

JTAG interface

Supports serial control interface, Motorola and Intel Non-Mul-

tiplexed interfaces and hardware control mode

Package:

IDT82V2082: 80-pin TQFP

•

DESCRIPTION:

The IDT82V2082 can be configured as a dual channel T1, E1 or J1 Line

Interface Unit. In receive path, an Adaptive Equalizer is integrated to

remove the distortion introduced by the cable attenuation. The

IDT82V2082 also performs clock/data recovery, AMI/B8ZS/HDB3 line

decoding and detects and reports the LOS conditions. In transmit path,

there is an AMI/B8ZS/HDB3 encoder, Waveform Shaper and LBOs.

There is one Jitter Attenuator, which can be placed in either the receive

path or the transmit path. The Jitter Attenuator can also be disabled. The

IDT82V2082 supports both Single Rail and Dual Rail system interfaces.

To facilitate the network maintenance, a PRBS/QRSS generation/detec-

tion circuit is integrated in the chip, and different types of loopbacks can

be set according to the applications. Four different kinds of line terminating

impedance, 75

Ω,

100

Ω,

110

Ω

and 120

Ω

are selectable on a per chan-

nel basis. The chip also provides driver short-circuit protection and internal

protection diode and supports JTAG boundary scanning. The chip can be

controlled by either software or hardware.

The IDT82V2082 can be used in LAN, WAN, Routers, Wireless Base

Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,

CSU/DSU equipment, etc.

INDUSTRIAL TEMPERATURE RANGES



The IDT logo is a registered trademark of Integrated Device Technology, Inc.

July 2004

DSC-6229/5

DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

TABLE OF CONTENTS

IDT82V2082 PIN CONFIGURATIONS .......................................................................................... 8

PIN DESCRIPTION ....................................................................................................................... 9

FUNCTIONAL DESCRIPTION .................................................................................................... 17

3.1

CONTROL MODE SELECTION ....................................................................................... 17

3.2

T1/E1/J1 MODE SELECTION .......................................................................................... 17

3.3

TRANSMIT PATH ............................................................................................................. 17

3.3.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 17

3.3.2 ENCODER ............................................................................................................. 17

3.3.3 PULSE SHAPER .................................................................................................... 17

3.3.3.1 Preset Pulse Templates .......................................................................... 17

3.3.3.2 LBO (Line Build Out) ............................................................................... 18

3.3.3.3 User-Programmable Arbitrary Waveform ................................................ 18

3.3.4 TRANSMIT PATH LINE INTERFACE..................................................................... 22

3.3.5 TRANSMIT PATH POWER DOWN ........................................................................ 23

3.4

RECEIVE PATH ............................................................................................................... 23

3.4.1 RECEIVE INTERNAL TERMINATION.................................................................... 23

3.4.2 LINE MONITOR ...................................................................................................... 24

3.4.3 ADAPTIVE EQUALIZER......................................................................................... 25

3.4.4 RECEIVE SENSITIVITY ......................................................................................... 25

3.4.5 DATA SLICER ........................................................................................................ 25

3.4.6 CDR (Clock & Data Recovery)................................................................................ 25

3.4.7 DECODER .............................................................................................................. 25

3.4.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 25

3.4.9 RECEIVE PATH POWER DOWN........................................................................... 25

3.4.10 G.772 NON-INTRUSIVE MONITORING ................................................................ 26

3.5

JITTER ATTENUATOR .................................................................................................... 27

3.5.1 JITTER ATTENUATION FUNCTION DESCRIPTION ............................................ 27

3.5.2 JITTER ATTENUATOR PERFORMANCE ............................................................. 27

3.6

LOS AND AIS DETECTION ............................................................................................. 28

3.6.1 LOS DETECTION ................................................................................................... 28

3.6.2 AIS DETECTION .................................................................................................... 29

3.7

TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 30

3.7.1 TRANSMIT ALL ONES ........................................................................................... 30

3.7.2 TRANSMIT ALL ZEROS......................................................................................... 30

3.7.3 PRBS/QRSS GENERATION AND DETECTION.................................................... 30

3.8

LOOPBACK ...................................................................................................................... 30

3.8.1 ANALOG LOOPBACK ............................................................................................ 30

3.8.2 DIGITAL LOOPBACK ............................................................................................. 30

3.8.3 REMOTE LOOPBACK............................................................................................ 30

3.8.4 INBAND LOOPBACK.............................................................................................. 32

3.8.4.1 Transmit Activate/Deactivate Loopback Code......................................... 32

3.8.4.2 Receive Activate/Deactivate Loopback Code.......................................... 32

DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

3.9

3.10

3.11

3.12

3.13

3.14

3.15

3.16

3.8.4.3 Automatic Remote Loopback .................................................................. 32

ERROR DETECTION/COUNTING AND INSERTION ...................................................... 33

3.9.1 DEFINITION OF LINE CODING ERROR ............................................................... 33

3.9.2 ERROR DETECTION AND COUNTING ................................................................ 33

3.9.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 34

LINE DRIVER FAILURE MONITORING ........................................................................... 34

MCLK AND TCLK ............................................................................................................. 35

3.11.1 MASTER CLOCK (MCLK) ...................................................................................... 35

3.11.2 TRANSMIT CLOCK (TCLK).................................................................................... 35

MICROCONTROLLER INTERFACES ............................................................................. 36

3.12.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 36

3.12.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 36

INTERRUPT HANDLING .................................................................................................. 37

5V TOLERANT I/O PINS .................................................................................................. 37

RESET OPERATION ........................................................................................................ 37

POWER SUPPLY ............................................................................................................. 37

PROGRAMMING INFORMATION .............................................................................................. 38

4.1

4.2

4.2.1 GLOBAL REGISTERS............................................................................................ 40

4.2.2 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 41

4.2.3 JITTER ATTENUATION CONTROL REGISTER ................................................... 41

4.2.4 TRANSMIT PATH CONTROL REGISTERS........................................................... 42

4.2.5 RECEIVE PATH CONTROL REGISTERS ............................................................. 44

4.2.6 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 46

4.2.7 INTERRUPT CONTROL REGISTERS ................................................................... 49

4.2.8 LINE STATUS REGISTERS ................................................................................... 52

4.2.9 INTERRUPT STATUS REGISTERS ...................................................................... 54

4.2.10 COUNTER REGISTERS ........................................................................................ 55

HARDWARE CONTROL PIN SUMMARY .................................................................................. 56

IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 58

6.1

JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 59

6.2

JTAG DATA REGISTER ................................................................................................... 59

6.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 59

6.2.2 BYPASS REGISTER (BR)...................................................................................... 59

6.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 59

6.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 59

TEST SPECIFICATIONS ............................................................................................................ 62

MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 74

8.1

SERIAL INTERFACE TIMING .......................................................................................... 74

8.2

PARALLEL INTERFACE TIMING ..................................................................................... 75

DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

LIST OF TABLES

Table-1

Table-2

Table-3

Table-4

Table-5

Table-6

Table-7

Table-8

Table-9

Table-10

Table-11

Table-12

Table-13

Table-14

Table-15

Table-16

Table-17

Table-18

Table-19

Table-20

Table-21

Table-22

Table-23

Table-24

Table-25

Table-26

Table-27

Table-28

Table-29

Table-30

Table-31

Table-32

Table-33

Table-34

Table-35

Table-36

Table-37

Table-38

Table-39

Table-40

Table-41

Table-42

Table-43

Table-44

Table-45

Table-46

Pin Description ................................................................................................................ 9

Transmit Waveform Value For E1 75

Ω

........................................................................ 19

Transmit Waveform Value For E1 120

Ω

...................................................................... 19

Transmit Waveform Value For T1 0~133 ft................................................................... 19

Transmit Waveform Value For T1 133~266 ft............................................................... 20

Transmit Waveform Value For T1 266~399 ft............................................................... 20

Transmit Waveform Value For T1 399~533 ft............................................................... 20

Transmit Waveform Value For T1 533~655 ft............................................................... 20

Transmit Waveform Value For J1 0~655 ft ................................................................... 21

Transmit Waveform Value For DS1 0 dB LBO.............................................................. 21

Transmit Waveform Value For DS1 -7.5 dB LBO ......................................................... 21

Transmit Waveform Value For DS1 -15.0 dB LBO ....................................................... 21

Transmit Waveform Value For DS1 -22.5 dB LBO ....................................................... 22

Impedance Matching for Transmitter ............................................................................ 22

Impedance Matching for Receiver ................................................................................ 23

Criteria of Starting Speed Adjustment........................................................................... 27

LOS Declare and Clear Criteria for Short Haul Mode ................................................... 28

LOS Declare and Clear Criteria for Long Haul Mode.................................................... 29

AIS Condition ................................................................................................................ 29

Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 30

EXZ Definition ............................................................................................................... 33

Interrupt Event............................................................................................................... 37

Global Register List and Map........................................................................................ 38

Per Channel Register List and Map .............................................................................. 39

ID: Device Revision Register ........................................................................................ 40

RST: Reset Register ..................................................................................................... 40

GCF: Global Configuration Register ............................................................................. 40

INTCH: Interrupt Channel Indication Register............................................................... 40

TERM: Transmit and Receive Termination Configuration Register .............................. 41

JACF: Jitter Attenuation Configuration Register ........................................................... 41

TCF0: Transmitter Configuration Register 0 ................................................................. 42

TCF1: Transmitter Configuration Register 1 ................................................................. 42

TCF2: Transmitter Configuration Register 2 ................................................................. 43

TCF3: Transmitter Configuration Register 3 ................................................................. 43

TCF4: Transmitter Configuration Register 4 ................................................................. 43

RCF0: Receiver Configuration Register 0..................................................................... 44

RCF1: Receiver Configuration Register 1..................................................................... 45

RCF2: Receiver Configuration Register 2..................................................................... 46

MAINT0: Maintenance Function Control Register 0...................................................... 46

MAINT1: Maintenance Function Control Register 1...................................................... 47

MAINT2: Maintenance Function Control Register 2...................................................... 47

MAINT3: Maintenance Function Control Register 3...................................................... 47

MAINT4: Maintenance Function Control Register 4...................................................... 48

MAINT5: Maintenance Function Control Register 5...................................................... 48

MAINT6: Maintenance Function Control Register 6...................................................... 48

INTM0: Interrupt Mask Register 0 ................................................................................. 49

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IDT82V2082PF

IDT82V2082PF概述

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