Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos-
sible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry
described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other
rights, of Integrated Device Technology, Inc.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is exe-
cuted between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its
safety or effectiveness.
Table of Contents
FEATURES ........................................................................................................................................................................ 1
DATA SLICER ..............................................................................................................................................................................................
CLOCK AND DATA RECOVERY ................................................................................................................................................................
3.7.1 Line Code Rule ...............................................................................................................................................................................
3.7.3 LOS Detection ................................................................................................................................................................................
3.8.1.1.1 Super Frame (SF) Format .............................................................................................................................
3.8.1.1.2 Extended Super Frame (ESF) Format ...........................................................................................................
3.8.1.1.3 T1 Digital Multiplexer (DM) Format (T1 only) ................................................................................................
3.8.1.1.4 Switch Line Carrier - 96 (SLC-96) Format (T1 only) ......................................................................................
3.8.1.2 Error Event And Out Of Synchronization Detection ..........................................................................................................
3.8.1.2.1 Super Frame (SF) Format .............................................................................................................................
3.8.1.2.2 Extended Super Frame (ESF) Format ...........................................................................................................
3.8.1.2.3 T1 Digital Multiplexer (DM) Format (T1 only) ................................................................................................
3.8.1.2.4 Switch Line Carrier - 96 (SLC-96) Format (T1 only) ......................................................................................
3.8.1.3 Overhead Extraction (T1 Mode SLC-96 Format Only) .....................................................................................................
3.8.2.1.3 CAS Signaling Multi-Frame ...........................................................................................................................
3.8.2.2 Error Event And Out Of Synchronization Detection ..........................................................................................................
3.8.2.2.1 Out Of Basic Frame Synchronization ............................................................................................................
3.8.2.2.2 Out Of CRC Multi-Frame Synchronization ....................................................................................................
3.8.2.2.3 Out Of CAS Signaling Multi-Frame Synchronization .....................................................................................
3.8.2.3.1 International Bit Extraction .............................................................................................................................
3.8.2.3.2 Remote Alarm Indication Bit Extraction .........................................................................................................
14
15
17
17
17
18
19
19
19
19
19
19
19
20
23
23
23
23
24
25
26
27
27
27
27
27
28
28
30
32
32
33
34
34
35
35
35
35
35
35
3.8
Table of Contents
i
March 22, 2004
IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.8.2.3.3 National Bit Extraction ...................................................................................................................................
3.8.2.3.4 National Bit Codeword Extraction ..................................................................................................................
3.8.2.3.5 Extra Bit Extraction ........................................................................................................................................
3.8.2.3.6 Remote Signaling Multi-Frame Alarm Indication Bit Extraction .....................................................................
3.8.2.3.7 Sa6 Code Detection Per ETS 300 233 ..........................................................................................................
3.8.2.4 V5.2 Link ..........................................................................................................................................................................
3.11.2 Two HDLC Modes ...........................................................................................................................................................................
ELASTIC STORE BUFFER ..........................................................................................................................................................................
RECEIVE PAYLOAD CONTROL .................................................................................................................................................................
RECEIVE SYSTEM INTERFACE .................................................................................................................................................................
3.17.2.5 Output On RSDn/MRSDA(MRSDB) & RSIGn/MRSIGA(MRSIGB) ..................................................................................
TRANSMIT SYSTEM INTERFACE ..............................................................................................................................................................
TRANSMIT PAYLOAD CONTROL ..............................................................................................................................................................
3.20.1.1.1 Super Frame (SF) Format .............................................................................................................................
3.20.1.1.2 Extended Super Frame (ESF) Format ...........................................................................................................
3.20.1.1.3 T1 Digital Multiplexer (DM) Format (T1 only) ................................................................................................
3.20.1.1.4 Switch Line Carrier - 96 (SLC-96) Format (T1 only) ......................................................................................
3.20.2.2 Two HDLC Modes ............................................................................................................................................................
3.20.6 All ‘Zero’s & All ‘One’s ...................................................................................................................................................................
3.20.7 Change Of Frame Alignment .........................................................................................................................................................
3.22.1 Line Code Rule ...............................................................................................................................................................................
3.22.3 All ‘One’s Insertion ........................................................................................................................................................................
WAVEFORM SHAPER / LINE BUILD OUT .................................................................................................................................................
3.24.2 Line Build Out (LBO) (T1 Only) .....................................................................................................................................................
LINE DRIVER ...............................................................................................................................................................................................
TESTING AND DIAGNOSTIC FACILITIES .................................................................................................................................................
3.27.2.1 System Loopback .............................................................................................................................................................
3.27.2.1.1 System Remote Loopback ............................................................................................................................
3.27.2.1.2 System Local Loopback ................................................................................................................................
3.27.2.3 Local Digital Loopback 1 ..................................................................................................................................................
3.27.2.5 Local Digital Loopback 2 ..................................................................................................................................................
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