Integrated Device Technology, Inc.
128K x 32
CMOS STATIC RAM
MODULES
DESCRIPTION:
IDT7MP4060
IDT7MP4095
FEATURES:
• High density 4 megabit static RAM modules
• Low profile 64-pin ZIP (Zig-zag In-line vertical Package),
64-lead, 72-lead SIMMs (Single In-line Memory Modules)
• Fast access time: 15ns (max.)
• Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
• Single 5V (±10%) power supply
• Multiple GND pins and decoupling capacitors for maxi-
mum noise immunity
• Inputs/outputs directly TTL compatible
• Gold plated fingers on the SIMM version
PIN CONFIGURATION – 7MP4095
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
GND
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
A
15
CS
2
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
14
CS
1
CS
3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
PD
0
- OPEN
PD
1
- OPEN
The IDT7MP4095/7MP4060 are 128K x 32 static RAM
modules constructed on an epoxy laminate (FR-4) substrate
using four 128K x 8 static RAMs in plastic SOJ packages. The
IDT7MP4095/7MP4060 are available with access times as
fast as 15ns with minimal power consumption.
The IDT7MP4095 is packaged in a 64-pin FR-4 ZIP (Zig-
zag In-line vertical Package) or a 64-lead SIMM (Single In-line
Memory Module). The IDT7MP4060 is packaged in a 72-lead
SIMM. The ZIP configuration allows 64 pins to be placed on
a package 3.65 inches long and 0.21 inches thick. At only 0.60
inches high, this low-profile package is ideal for systems with
minimum board spacing, while the SIMM configuration allows
use of edge mounted sockets to secure the module.
All inputs and outputs of the IDT7MP4095/7MP4060 are
TTL compatible and operate from a single 5V supply. Full
asynchronous circuitry requires no clocks or refresh for opera-
tion and provides equal access and cycle times for ease of
use.
FUNCTIONAL BLOCK DIAGRAM
CS
1
CS
2
CS
3
CS
4
ADDRESS
WE
OE
17
128K x 32
RAM
CS
4
A
16
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
NC
OE
8
8
8
8
3147 drw 01
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
I/O
0-31
PIN NAMES
I/O
0
–
31
A
0
–
16
Data Inputs/Outputs
Addresses
Chip Selects
Write Enable
Output Enable
Power
Ground
No Connect
3147 tbl 01
CS
1
–
4
WE
OE
V
CC
GND
NC
ZIP, SIMM
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996
Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
SEPTEMBER 1996
DSC-3147/7
7.09
1
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION – 7MP4060
NC
PD
3
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
I/O
7
WE
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
Parameter
(1)
Input Capacitance
(Data and
CS
)
Input Capacitance
(Address,
WE
,
OE
)
Output Capacitance
Conditions
V
(IN)
= 0V
V
(IN)
= 0V
V
(OUT)
= 0V
Max.
12
40
12
Unit
pF
pF
pF
3147 tbl 04
A
14
CS
1
CS
3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
NC
PD
2
GND
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
A
15
CS
2
CS
4
PD
0
- OPEN
PD
1
- OPEN
PD
2
- OPEN
PD
3
- GND
C
IN(D)
C
IN(A)
C
OUT
NOTE:
1. This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5.0
0
—
—
Max.
5.5
0
5.8
0.8
Unit
V
V
V
V
3147 tbl 05
A
16
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
NC
NC
NC
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
NC
NC
3147 drw 13
NOTE:
1. V
IL
(min) = –3.0V for pulse width less than 10ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Ambient
Temperature
0°C to +70°C
GND
0V
V
CC
5.0V
±
10%
3147 tbl 06
TRUTH TABLE
Mode
Standby
Read
Write
Read
CS
OE
WE
Output
High Z
DATA
OUT
DATA
IN
High-Z
Power
Standby
Active
Active
Active
3147 tbl 02
H
L
L
L
X
L
X
H
X
H
L
H
SIMM
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
A
T
BIAS
T
STG
I
OUT
Rating
Terminal Voltage with
Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
DC Output Current
Value
–0.5 to +7.0
0 to +70
–10 to +85
–55 to +125
50
Unit
V
°C
°C
°C
mA
NOTES:
3147 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
7.09
2
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±10%,
T
A
= 0°C to +70°C)
Symbol
|I
LI
|
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage
(Data and
CS
)
Input Leakage
(Address,
WE
, and
OE
)
Output Leakage
Output Low
Output High
V
CC
= Max.;
CS
= V
IH
, V
OUT
= GND to V
CC
V
CC
= Min., I
OL
= 8mA
V
CC
= Min., I
OH
= –4mA
—
—
2.4
10
0.4
—
µA
V
V
V
CC
= Max.; V
IN
= GND to V
CC
—
40
µA
Test Conditions
V
CC
= Max.; V
IN
= GND to V
CC
Min.
—
Max.
10
Unit
µA
Symbol
I
CC
I
SB
I
SB1
Parameter
Dymanic Operating
Current
Standby Supply
Current
Full Standby
Supply Current
Test Conditions
f = f
MAX
;
CS
= V
IL
V
CC
= Max.; Output Open
CS
≥
V
IH,
V
CC
= Max.
Outputs Open, f = f
MAX
CS
≥
V
CC
– 0.2V; f = 0
V
IN
> V
CC
– 0.2V or < 0.2V
Max.
760
160
60
Unit
mA
mA
mA
3147 tbl 07
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
3147 tbl 08
+5 V
+5 V
480
Ω
DATA
OUT
255Ω
DATA
OUT
30 pF*
255Ω
480
Ω
5 pF*
* Includes scope and jig.
Figure 1. Output Load
3147 drw 03
Figure 2. Output Load
(for tOLZ, tOHZ, tCHZ, tCLZ,
tWHZ, tOW)
7.09
3
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
±10%,
T
A
= 0°C to +70°C)
-15
Symbol Parameter
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ(1)
t
OE
t
OLZ
(1)
(1)
(1)
-20
Max.
—
15
15
—
8
—
8
8
—
—
15
—
—
—
—
—
—
8
—
—
—
Min.
20
—
—
3
—
0
—
—
3
0
—
20
18
18
0
18
3
—
12
0
3
Max.
—
20
20
—
10
—
12
12
—
—
20
—
—
—
—
—
—
13
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3147 tbl 10
Min.
15
—
—
3
—
0
—
—
3
0
—
15
12
12
0
12
0
—
10
0
3
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low Z
Output Enable to Output Valid
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write Enable to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
t
CHZ
t
OH
t
PU
t
PD
t
OHZ
(1)
(1)
Write Cycle
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ(1)
t
DW
t
DH
t
OW(1)
NOTE:
1. This parameter is guaranteed by design, but not tested.
7.09
4
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
t
RC
ADDRESS
t
AA
OE
t
OE
CS
t
OH
t
OLZ
(5)
t
ACS
t
CLZ
(5)
t
OHZ
(5)
t
CHZ
(5)
DATA
OUT
3147 drw 04
TIMING WAVEFORM OF READ CYCLE NO. 2
(1,2,4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA VALID
t
OH
DATA VALID
3147 drw 05
TIMING WAVEFORM OF READ CYCLE NO. 3
(1,3,4)
CS
t
ACS
t
CLZ (5)
DATA
OUT
t
CHZ
(5)
3147 drw 06
NOTES:
1.
WE
is High for Read Cycle.
2. Device is continuously selected.
CS
= V
IL
.
3. Address valid prior to or coincident with
CS
transition low.
4.
OE
= V
IL
.
5. Transition is measured
±200mV
from steady state. This parameter is guaranteed by design, but not tested.
7.09
5
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